Imperial College London > Talks@ee.imperial > CAS Talks > Validating the (Memory) Persistency Semantics of Intel-x86 Architecture

Validating the (Memory) Persistency Semantics of Intel-x86 Architecture

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Memory persistency models prescribe the order Non-Volatile Memory (NVM) `writes’ become durable. This allows programmers to reason about guarantees on recovery-correctness. We consider the problem of validating empirically the formalisation of the persistency semantics of programs interfacing with NVM . To explore recoverability behaviour with respect to durability and ordering in normal operation (instead of simulating power-loss crashes while the workload is running), we monitor the DDR4 bus traffic in real time by interposing a monitoring object between CPU and main memory in the DDR bus. By conducting validity litmus tests on several examples of persistent programs, we judge the goodness of the Px86 (‘persistent x86’) model and confirm that the assumptions underlying the model are justifiable.

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