The Semantics of Shared Memory in CPU/FPGA Systems

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• Dan Iorga (Imperial College)
• Monday 23 November 2020, 16:00-17:00
• Teams.

If you have a question about this talk, please contact George A Constantinides.

Fundamental limits of hardware scaling mean that modern computing systems feature an increasing variety of heterogeneous parallel computing units. Applications must be partitioned across these units to run in a performant and energy-efficient manner. To run reliably, applications must issue sufficient synchronization operations when accessing shared memory. This is challenging: the rules governing shared-memory behaviour in modern systems are often under-specified, especially when compute-units expose a low-level interface to shared memory and are rarely specified in a formal manner that facilitates rigorous reasoning.

Our work takes steps to address this by providing rigorous formal foundations for such emerging systems, to support programmers, compiler writers and designers of analysis tools in navigating the complexities of these systems and unlocking their potential efficiencies. As a case study, we focus on Intel platforms that combine Intel FPG As with multicore Xeon CPUs. Via a detailed study of documentation and empirical testing, we show that the low-level shared-memory interface for FPGA computations allows a variety of complex behaviours, e.g. allowing sequential computation streams to observe stale values. including many not seen in mainstream CPUs.

This talk is part of the CAS Talks series.

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