Area Evaluation of Memory-based PLD Architecture by Mapping Arithmetic Circuits

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• Dr. Kazuya Tanigawa, Department of Computer Enginnering Hiroshima City University, Japan
• Thursday 16 February 2012, 11:00-13:00
• Room 611 (Gabor Seminar Room), Electrical and Electronic Engineering.

If you have a question about this talk, please contact Justin Wong.

In this presentation, I will introduce a Memory-based Programmable Logic Device (MPLD) which goal is to improve the chip area efficiency of conventional reconfigurable device. An MPLD consists of multiple-output look-up tables (MLUTs) that can be used as logic and/or routing elements, whereas FPGA consists of LUTs (logic elements) and switch blocks (routing elements). MPL Ds contain logic circuits more efficiently than FPG As because of their flexibility and area efficiency. In this presentation, I will show the comparison results of the required chip area for mapping several arithmetic units on MPLD and FPGA .

This talk is part of the Justin Wong's list series.

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• Room 611 (Gabor Seminar Room), Electrical and Electronic Engineering

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