Visualisation in Circuit Design

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• Dr Ian Jones, Sun Labs, Oracle, USA
• Friday 14 May 2010, 14:00-14:50
• Gabor Seminar Room (Room 611).

If you have a question about this talk, please contact Professor Peter Cheung.

Visualisation techniques can enhance the understanding of circuit behaviour and their operating environment. Visualisation enables exploration of massive quantities of data from a high-level overview right down to low-level detail. I will present some short animated movies that address clock domain crossing circuits, and whole-chip clock distribution. These visualisation aids are used to tune and debug designs, and have uncovered problems not found by the standard development tools.

Bio ====

Ian completed his PhD in Electrical Engineering at Imperial College, London in 1986. He was introduced to asynchronous circuit and systems design while working with Sutherland, Sproull and Associates, Inc. Ian then went to work in the Advanced Technology Group at Apple Computer. At Apple he helped develop a software-programmable gate array chip prototype – one of his few clocked chip designs. He joined Sun Labs in 1992, where he has continued research work focusing on high speed asynchronous circuits and synchronisers. Ian works closely with chip designers in the product division, applying asynchronous circuit techniques to help improve their products.

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