Scaling Up Modulo Scheduling For High-Level Synthesis

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• Leandro de Souza Rosa
• Tuesday 14 November 2017, 16:00-17:00
• Seminar Room 909b, EEE Building.

If you have a question about this talk, please contact Wiesia R Hsissen.

A key optimisation towards achieving high-performance acceleration kernels is loop pipelining, which is also responsible for the majority of the compilation time in HLS tools. A new modulo scheduling algorithm is proposed, which reformulates the classical scheduling problem and leads to a reduction the number of the integer linear problems solved leading to large computational savings. Moreover, the proposed approach has a controlled trade-off between solution quality and computation time.

This talk is part of the Circuits and Systems Group: Internal Seminars series.

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• Circuits and Systems Group: Internal Seminars
• Seminar Room 909b, EEE Building

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