Imperial College London > Talks@ee.imperial > Featured talks > HiPEDS Seminar - Big graphs on big machines

HiPEDS Seminar - Big graphs on big machines

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Oracle’s largest SPARC M7 system provides 4096 hardware threads spread over 16 sockets in one cache-coherent address space.I will talk about our experience tuning graph analytics workloads to run well on this system, and how we went from an implementation that stopped scaling at around 200 threads to a version that provides super-linear speed-ups on PageRank and SSSP running on 1TB+ inputs over the full machine. I will focus on the interactions between the threads and the memory system, and the lessons we learned in terms of how to allocate memory and distribute work on these large NUMA systems.

Bio: Tim Harris leads the Oracle Labs group in Cambridge, UK. His research interests span multiple layers of the stack, including parallel programming, VMM / OS / runtime-system interaction, and opportunities for specialized architecture support for particular workloads. He has also worked on the implementation of software transactional memory for multi-core computers, and the design of programming language features based on it. He is a co-author of the Morgan Claypool book Transactional Memory. Tim has a BA and PhD in computer science from Cambridge University Computer Laboratory. He was on the faculty at the Computer Laboratory from 2000-2004 where he led the department’s research on concurrent data structures and contributed to the Xen virtual machine monitor project. He was at Microsoft Research from 2004, and then joined Oracle Labs in 2012.

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