Synchroniser Behaviour and Analysis

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• Dr Ian Jones, Sun Microsystems Lab
• Wednesday 06 May 2009, 14:30-17:00
• Level 9 Seminar Room, EE Dept..

If you have a question about this talk, please contact Professor Peter Cheung.

Transferring data between independent clock domains is inherently error prone. Synchroniser circuits are employed at these interfaces to improve the reliability of the data transfers. Higher operating frequencies require improved synchronisers and estimating their reliability is important to achieve sufficiently low error rates, However, synchroniser characterisation is non-trivial. The exponential response to parameter changes makes this task a challenge, which is further hampered by numerical instability and precision limitations of circuit simulators. The analysis of multi-stage synchronisers is extremely difficult due to the compounding of these exponential factors. I will present results and discoveries from analyzing a variety of synchroniser circuits, and show some problematic circuit behaviours that can arise from synchroniser operation.

Bio:

Ian W. Jones in the VLSI Research group of Sun Microsystems Laboratories. He has a PhD from Imperial College, 1986. He has previously worked with Sutherland, Sproull, and Associates, and in the Advanced Technology Group at Apple Computer. He has over twenty years experie its and systems design.

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