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Rapid Prototyping of Embedded VLSI Systems

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In this talk, we focus on tools and methodologies for design, simulation, and prototyping of VLSI , FPGA and reconfigurable processors. This talk presents a rapid prototyping design methodology for the design and implementation of digital signal processing (DSP) algorithms and systems on embedded hardware platforms, such as cellular telephones and wireless networks. The process begins with a high level algorithmic description in a design and simulation language and then is mapped and synthesized to a number of targets including ASIC , FPGA, and DSP systems. The challenge is to exploit the data parallelism in the algorithms to achieve high performance in low-power systems. At Rice University, we are building a wireless open access reseach platform systems testbed, called WARP , that supports end-to-end prototyping research. The research goal is to explore the complexity and performance of signal processing architectures for high data rate wireless systems using multiple transmit and receive antennas. The testbed includes high performance DSP processors integrated with high density FPGA devices. These digital devices are in turn connected via high speed A/D and D/A data converters to 2.4 GHz radios. The lab also contains wireless channel emulators that allow the study of typical wireless channels observed in urban and rural environments. In this talk, we will present the tools and design methodologies in the context of embedded systems design. We will describe an example receiver system prototype using tools from the Mathworks, Mentor Graphics, National Instruments, Texas Instruments, and Xilinx. Application of these design methodologies to the design of future DSP systems will shorten development time and improve the efficiency of the systems.

Brief bio Joseph R. Cavallaro (S’78, M’82, SM’05) received the B.S. degree from the University of Pennsylvania, Philadelphia, Pa, in 1981, the M.S. degree from Princeton University, Princeton, NJ, in 1982, and the Ph.D. degree from Cornell University, Ithaca, NY, in 1988, all in electrical engineering. From 1981 to 1983, he was with AT&T Bell Laboratories, Holmdel, NJ. In 1988, he joined the faculty of Rice University, Houston, TX, where he is currently a Professor of electrical and computer engineering. His research interests include computer arithmetic, VLSI design and microlithography, and DSP and VLSI architectures for applications in wireless communications. During the 1996–1997 academic year, he served at the National Science Foundation as Director of the Prototyping Tools and Methodology Program. He was a Nokia Foundation Fellow and a Visiting Professor at the University of Oulu, Finland in 2005 and continues his affiliation there as an Adjunct Professor. He is currently the Director of the Center for Multimedia Communication at Rice University. He is a Senior Member of the IEEE and a Member of the IEEE SPS TC on Design and Implementation of Signal Processing Systems and the IEEE CAS TC on Circuits and Systems for Communications. He is currently an Associate Editor of the IEEE Transactions on Signal Processing, the IEEE Signal Processing Letters, and the Journal of Signal Processing Systems. He was Co-chair of the 2004 Signal Processing for Communications Symposium at the IEEE Global Communications Conference and General/Program Co-chair of the 2003, 2004, and 2011 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP), General/Program Co-chair for the 2012, 2014 ACM /IEEE GLSVLSI , and Finance Chair for the 2013 IEEE GlobalSIP conference.

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