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High-Level Synthesis Revisited: Progress and Applications

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High-level synthesis has a long history dated back to 1980s with contributions from many in the field of electronic design automation. But its acceptance has been limited. With the goal of automatically synthesizing circuits that can tolerate long wire latency, my group at UCLA revisited the high-level synthesis problem in early 2000s. We developed a platform-based high-level synthesis system, named xPilot, which provides advanced behavioral synthesis capability for compiling C, C++, or SystemC applications to high quality RTL code optimized for a given FPGA or ASIC platform. In the past decade, our research in this area led to a number of algorithmic innovations, such as scheduling based on the system of difference constraints, extraction of behavior-level don’t cares, scheduling with soft constraints, automatic memory partitioning, pattern mining and pattern-based synthesis, etc. The xPilot system was licensed AutoESL Design Technologies, a UCLA spin-off, in 2006, and became the basis of AutoPilot tool developed by AutoESL. With further development and refinement at AutoESL, AutoPilot is able to produce RTL results comparable or better than manual RTL designs for many applications (e.g. see BDTI evaluation report at ). AutoESL had a number of large semiconductor and IT companies as its customers, and was acquired by Xilinx in January 2011. Xilinx is now making the AutoESL tool available to all its customers.

In this talk, I shall discuss some of the algorithmic innovations we had in xPilot/AutoPilot, and the results in real life designs. If time permits, I shall also report our current effort in the Center for Domain-Specific Computing on developing an accelerator-rich architecture (where automated C-to-RTL synthesis plays an important role) for better energy efficiency. Such architectures present many new challenges and opportunities, such as accelerator scheduling, sharing, memory hierarchy optimization, and efficient compilation and runtime support. In this talk, I shall present the results and ongoing research in these areas in the Center for Domain-Specific Computing.

Speaker Bio ========

JASON CONG received his B.S. degree in computer science from Peking University in 1985, his M.S. and Ph. D. degrees in computer science from the University of Illinois at Urbana-Champaign in 1987 and 1990, respectively. Currently, he is a Chancellor’s Professor at the Computer Science Department of University of California, Los Angeles, the director of Center for Domain-Specific Computing (CDSC), and co-director of the VLSI CAD Laboratory. He served as the department chair from 2005 to 2008. Dr. Cong’s research interests include synthesis of VLSI circuits and systems, programmable systems, novel computer architectures, nano-systems, and highly scalable algorithms. He has over 350 publications in these areas, including six best paper awards. He was elected to an IEEE Fellow in 2000 and ACM Fellow in 2008. Dr. Cong is the recipient of the 2010 IEEE Circuits and System (CAS) Society Technical Achievement Award “For seminal contributions to electronic design automation, especially in FPGA synthesis, VLSI interconnect optimization, and physical design automation.”

Dr. Cong has graduated 27 PhD students. A number of them are now faculty members in major research universities, including Georgia Tech., Purdue, SUNY Binghamton, UCLA , UIUC, and UT Austin. Others are taking key R&D or management positions in major EDA /computer/semiconductor companies, or being founding members of high-tech startups. He was a co-founder of Aplus Desgin Technologies (acquired by Magma, now part of Synopsys, in 2003) and AutoESL Design Technologies (acquired by Xilinx in 2011).

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