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Reliability of Wave Pipelining for NoC and FPGA

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Networks-on-Chip and FPG As both require a programmable interconnect structure where high-bandwidth, low-latency communication is key to performance. Wave pipelining meets this requirement—by sending data in waves through a logic network, and carefully timing the release of new data, maximum bandwidth and minimum latency can be achieved when everything is ideal. However, the real world is never ideal. Noise sources and unpredictable timing variation leads to serious performance degradation of wave-pipelined circuits. Accounting for noise, we will show that traditional synchronous circuits with registers offer higher bandwidth and are more reliable than wave pipelining. However, reliability and bandwidth can be improved by compensating for the main source of non-ideality, accumulated timing jitter, through the use of surfing and distributed asynchronous FIF Os. To estimate reliability of these circuits, we have devised new techniques based upon statistical timing.


Guy Lemieux is an Assistant Professor in the Department of Electrical and Computer Engineering at the University of British Columbia in Vancouver, British Columbia, Canada. His main research is in the design of FPG As and CAD tools. His interests include FPGA architecture and CAD , FPGA and VLSI circuit design, computer architecture, and parallel computing systems. His work on interconnect design for FPG As resulted in a book, published in November 2003. He received a Best Paper Award at the 2004

IEEE International Conference on Field-Programmable Technology. He received a Bronze Leaf Certificate paper award at the 2008 CMC Microsystems and Nanoelectronics Research Conference and a Best Poster Award at the 2009 BCNet Conference. He received his BASc, MASc, and PhD degrees from the University of Toronto. In this past life, he helped build a 64-CPU shared-memory multiprocessor called NUM Achine at Toronto. The system was built entirely from scratch out of FPG As, MIPS R4400 CP Us, memories, FIF Os, bus tranceivers, and lots of FR4 .

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