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Introduction of research activities on reconfigurable systems

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The talk introduces an overview of the speaker’s research activities including self reconfigurable architecture, autonomous repairing reconfigurable device, programmable logic for SoC, and context-switching reconfigurable architecture.

Self reconfigurable architecture: Configurable hardwares have evolved its “reconfigurablility” in generations and now can be reconfigured dynamically. We explored an extreme end of such evolutions where a circuit configured configures the circuit. An self-reconfigurable architecture named Plastic Cell Architecture (PCA) was proposed by Nippon Telegraph and Telephone Corp (NTT) in 1997 and the project was promoted by NTT , Kyoto Univ, Aizu Univ, and others. The talk introduces the concept and brief overview of architecture, device prototyping, CAD tools, applications, and so on, promoted in Kyoto Univ.

Autonomous repairing reconfigurable device: A bit of information may be flipped over in error, more frequently, for example, in outer space. For configurable device, that implies not only corruption of data but also unforeseen trouble in the circuit. However, easily-changed means easily-repaired. The talk introduces the concept and architecture of autonomous repairing cell promoted in Kyoto Univ, which detects and repairs a bit-flip in the circuit configuration running, without halt of the system.

Programmable logic for SoC: Recent SoC normally has CPUs, DSPs, hardwired IPs. Some programmable logic part is still needed but may not concern others’ job. ePLX (embedded programmable logic matrix) is a simple programmable logic fabric proposed to be embedded in such SoCs by Renesas Technology Corp and Ritsumeikan Univ. The talk introduces the architecture and overview of CAD tools for ePLX promoted in Ritsumeikan Univ.

Context-switching reconfigurable architecture: Dynamic reconfiguration is a key concept of recent generation of reconfigurable devices. Context switching is an efficient mechanism for dynamic reconfiguration where the reconfigurable resource has multiple banks of configuration memory and the circuit can be switched from one to another. DAPDNA is a reconfigurable processor developed by IP Flex Inc, Japan which consists of a RISC processor and a context-switching PE array. The talk introduces the concept of context switching, the architecture of DAPDNA , and outline of a launching project in Ritsumeikan Univ.

Dr. Tomonori Izumi an academic visitor to digital circuit and systems group, ICL Ritsumeikan Univ – Synthesis Corp –

He received his B.E. degree in Computer Science and M.E. and Ph.D. degrees in Electrical and Electronic Engineering all from Tokyo Institute of Technology, Japan, in 1992, 1994, and 1998, respectively. From 1998 to 2005, he was a research associate at Department of Communications and Computer Engineering, Graduate School of Informatics, Kyoto University, Japan. Since 2005, he has been an associate professor at Department of VLSI System Design, Ritsumeikan University, Japan. Concurrently, he has also been a chief engineer at Synthesis Corporation since 1998. His current research interests are in applications and design methodologies of dynamically reconfigurable systems. He is appointed as a organizing member of the technical committee on reconfigurable systems, the Institute of Electronics, Information and Communication Engineers, Japan, since 2007.

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