SPICE^2 - A Spatial Parallel Architecture for Accelerating the SPICE Circuit Simulator

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• Nachiket Kapre (Imperial College London)
• Friday 12 November 2010, 14:00-15:00
• Mahanakorn Lab, L9, EEE.

If you have a question about this talk, please contact George A Constantinides.

Nachiket Kapre is an Imperial College Junior Research Fellow, who has just started his 3-year research term in the Circuits and Systems Group. He recently obtained his PhD from Caltech, on the area of his talk.

Talk Abstract:

Spatial processing of sparse, irregular floating-point computation using a single FPGA enables up to an order of magnitude speedup (mean 2.8X speedup) over a conventional microprocessor for the SPICE circuit simulator. We deliver this speedup using a hybrid parallel architecture that spatially implements the heterogeneous forms of parallelism available in SPICE . We decompose SPICE into its three constituent phases: Model-Evaluation, Sparse Matrix-Solve, and Iteration Control and parallelize each phase independently. We exploit data-parallel device evaluations in the Model-Evaluation phase, sparse dataflow parallelism in the Sparse Matrix-Solve phase and compose the complete design in streaming fashion. We name our parallel architecture SPICE2 : Spatial Processors Interconnected for Concurrent Execution for accelerating the SPICE circuit simulator. We program the parallel architecture with a high-level, domain-specific framework that identifies, exposes and exploits parallelism available in the SPICE circuit simulator. This design is optimized with an auto-tuner that can scale the design to use larger FPGA capacities without expert intervention and can even target other parallel architectures with the assistance of automated code-generation. This FPGA architecture is able to outperform conventional processors due to a combination of factors including high utilization of statically-scheduled resources, low-overhead dataflow scheduling of fine-grained tasks, and overlapped processing of the control algorithms. We demonstrate that we can independently accelerate Model-Evaluation by a mean factor of 6.5X(1.4—23X) across a range of non-linear device models and Matrix-Solve by 2.4X(0.6—13X) across various benchmark matrices while delivering a mean combined speedup of 2.8X(0.2—11X) for the two together when comparing a Xilinx Virtex-6 LX760 (40nm) with an Intel Core i7 965 (45nm). With our high-level framework, we can also accelerate Single-Precision Model-Evaluation on NVIDIA GP Us, ATI GP Us, IBM Cell, and Sun Niagara 2 architectures. We expect approaches based on exploiting spatial parallelism to become important as frequency scaling slows down and modern processing architectures turn to parallelism (\eg multi-core, GPUs) due to constraints of power consumption. This thesis shows how to express, exploit and optimize spatial parallelism for an important class of problems that are challenging to parallelize.

This talk is part of the Featured talks series.

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• Andrea Picciau's list
• COMMSP & CP list
• COMMSP Seminar
• Featured talks
• Mahanakorn Lab, L9, EEE
• SAP Talks

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