Imperial College London > Talks@ee.imperial > Featured lists > Adaptive Error Control for Networks-on-Chip Links

Adaptive Error Control for Networks-on-Chip Links

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Existing methods to manage transient and permanent errors in NOC links typically handle these errors independently at various layers in the NOC protocol stack. This separated error management results in large hardware overheads. In this work, we propose a cooperative cross-layer error control method to manage transient and permanent errors in NOC links. To reduce energy overhead, configurable error control coding adapts the coding strength or number of redundant wires to varying noise conditions, achieving required error detection/correction capabilities. Infrequently used redundant wires are utilized as spare wires to replace permanently unusable links. Case studies implementing the proposed techniques show that our method significantly reduces the energy per useful packet as well as average latency, compared to previous works.

Speaker Bio: Prof Paul Ampadu received the PhD degree in electrical and computer engineering from Cornell University, NY USA in 2004. From 2001 to 2002 and in the summers of 1999 and 2000, he investigated design and implementation of energy-efficient VLSI signal processing blocks at the IBM T . J. Watson Research Center. His research interests are in energy-efficient and fault-tolerant networks-on-chip. Dr. Ampadu is the author or co-author of dozens of scholarly articles, and serves on the program committees of several international conferences. Currently he is an associate professor of electrical & computer engineering, directs the Embedded Integrated Systems-on-chip (EdISon) research group, and co-directs the Ballistic Deflection Transistor (BDT) group at the University of Rochester. Dr. Ampadu received a 2010 Black Engineer of the Year Special Recognition Award, a University of Rochester Charles Drew Professor’s Choice Award, and the National Science Foundation CAREER award.

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