Imperial College London > Talks@ee.imperial > Room 611 (Gabor Seminar Room), Electrical and Electronic Engineering

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Area Evaluation of Memory-based PLD Architecture by Mapping Arithmetic Circuits

UserDr. Kazuya Tanigawa, Department of Computer Enginnering Hiroshima City University, Japan.

HouseRoom 611 (Gabor Seminar Room), Electrical and Electronic Engineering.

ClockThursday 16 February 2012, 11:00-13:00

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