Acceleration of Top-k ListNet Training Using FPGA

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• Qiang (Imperial College)
• Monday 18 December 2017, 15:00-16:00
• Level 9 Seminar Room, EE Dept..

If you have a question about this talk, please contact George A Constantinides.

ListNet is a promising technique for ranking objects by constructing and training ranking models, in this talk we explore the novel application of model training for ListNet on a FPGA device. Often model training needs to happen within a low latency, however, in ListNet the time complexity scales quadratically with the number of documents being ranked limiting it to small problem sizes. Existing work tackles this by trading ranking accuracy for performance, but reducing accuracy is undesirable. In this talk, we overcome the high time complexity by rewriting the model and accelerating the execution, this allows for accuracy to be maintained while meeting latency constraints. To demonstrate this, we apply our implementation to the MQ 2008 benchmark dataset and we demonstrate that it achieves better accuracy improvement over commercial approach for the same time.

This talk is part of the CAS Talks series.

This talk is included in these lists:

• Andrea Picciau's list
• CAS Talks
• Circuits and Systems Group: Internal Seminars
• Level 9 Seminar Room, EE Dept.

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