Designing Parameterised Application Specific SDRAM controllers from Affine Loop Nests

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• Samuel Bayliss (Imperial College)
• Thursday 03 June 2010, 16:00-17:00
• Level 9 Mahanakorn Lab., EE Dept..

If you have a question about this talk, please contact George A Constantinides.

Many compute-intensive applications have data-sets larger than the internal memory available on contemporary FPG As. Hardware designs must therefore incorporate external memory interfaces to fetch data from off-chip memory. The current controller IP-based approach to SDRAM interfacing assumes no prior knowledge of the sequence of addresses requested from external memory and treats each transaction as if it’s timing is non-deterministic. This talk reports on progress in developing novel application-specific memory controllers for embedded and HPC applications, and presents early results which suggest such an approach can be used to bound memory power and provide a guarantee of meeting system memory performance requirements at compile time.

This talk is part of the CAS Talks series.

This talk is included in these lists:

• Andrea Picciau's list
• CAS Talks
• Circuits and Systems Group: Internal Seminars
• Level 9 Mahanakorn Lab., EE Dept.

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