Imperial College London > Talks@ee.imperial > CAS Talks > Tile Size Selection for Optimized Memory Reuse in High-Level Synthesis
Log inImperial users Other users No account?Information onFinding a talk Adding a talk Syndicating talks Who we are Everything else |
Tile Size Selection for Optimized Memory Reuse in High-Level SynthesisAdd to your list(s) Download to your calendar using vCal
If you have a question about this talk, please contact George A Constantinides. High-level synthesis (HLS) is well capable of generating control and computation circuits for FPGA accelerators, but still requires sufficient human effort to tackle the challenge of memory and communication bottlenecks. One important approach for improving data locality is to apply loop tiling on memory-intensive loops. Loop tiling is a well-known compiler technique that partitions the iteration space of a loop nest into chunks (or ‘tiles’) whose associated data can fit into size-constrained fast memory. The size of the tiles, which can significantly affect the memory requirement, is usually determined by partial enumeration. In this paper, we propose an analytical methodology to select a tile size for optimized memory reuse in HLS . A parametric polyhedral model is introduced to capture memory usage analytically for arbitrary tile sizes. To determine the tile size for data reuse in constrained on-chip memory, an algorithm is then developed to optimize over this model, using non-linear solvers to minimize communication overhead. Experimental results on three representative loops show that, compared to random enumeration with the same time budget, our proposed method can produce tile sizes that lead to a 75% average reduction in communication overhead. Two case studies of the convolutional layers in CNN with real hardware prototyping also demonstrates the benefits of using the proposed tile size selection. This talk is part of the CAS Talks series. This talk is included in these lists:Note that ex-directory lists are not shown. |
Other listsType the title of a new list here Complexity & Networks Group Control and Power SeminarsOther talksDissolvable Tattoo Electronics for Biomedicine Nonconvex Geometry of Low-Rank Optimizations |