FPGA -Based Acceleration of RankNet for Web Search

Add to your list(s) Download to your calendar using vCal

• Qiang Li
• Monday 24 April 2017, 15:00-16:00
• Level 9 Seminar Room, EE Dept..

If you have a question about this talk, please contact George A Constantinides.

In modern Web search engines, machine learning algorithms are leveraged to build innovative and effective ranking models. Neural Network (NN)-based algorithm is the most popular one among these algorithms. With the increasing scale of the Web, the training time for NN algorithm needs to be reduced. However, those improvements cannot be obtained from general-purpose systems because of non-programmable hardware features. Both FPG As and GPUs offer the potential to solve this problem, but the power consumption of GPU is a dominant challenge for conventional datacentre servers, so we pay attention to FPG As.

In this talk, I’ll present an FPGA -based solution to provide high computing performance for Ranknet, which is a pairwise approach. A compact deep pipeline is used to reduce the complexity of BackPropagation computation. The data format is also designed to fulfill BRAM requirement. The relation between time consumption and the number of hidden nodes, the relation between accuracy and the number of hidden nodes will be discussed. We hope the solution will be useful for other Neural Network algorithms, such as ListNet. We hope to utilize this solution to improve accuracy of ListNet without increasing training time.

This talk is part of the CAS Talks series.

This talk is included in these lists:

• Andrea Picciau's list
• CAS Talks
• Circuits and Systems Group: Internal Seminars
• Level 9 Seminar Room, EE Dept.

Note that ex-directory lists are not shown.