Input-dependent Static Timing Analysis (iSTA)

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• Andrea Suardi (Imperial College)
• Monday 08 May 2017, 15:00-16:00
• Level 9 Seminar Room, EE Dept..

If you have a question about this talk, please contact George A Constantinides.

Conventional Static Timing Analysis (STA) has been embraced for many years to compute the expected timing of digital circuits. This is achieved by leveraging on the circuit topology and the timing information of individual nodes and edges. Ignoring the logic functionality of the circuit results in a conservative approach which computes only the worst timing across all the possible input transitions and does not detect false-paths natively. In this talk, I’ll introduce an approach called iSTA (input-dependent STA ) which simultaneously addresses these concerns. iSTA generates a circuit path-delay distribution, where each path-delay has an associated probability, rather than a single worst-case timing value. This results in a significant higher computational cost compared to the classical STA approach. For this reason, I’ll also present a mathematically rigorous way to approximate the path-delay distribution, leading to a controlled trade-off between solution accuracy and analysis time.

This talk is part of the CAS Talks series.

This talk is included in these lists:

• Andrea Picciau's list
• CAS Talks
• Circuits and Systems Group: Internal Seminars
• Level 9 Seminar Room, EE Dept.

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