Imperial College London > Talks@ee.imperial > CAS Talks > Implementing an arbitrary number of iterations to arbitrary precision

Implementing an arbitrary number of iterations to arbitrary precision

Add to your list(s) Download to your calendar using vCal

If you have a question about this talk, please contact George A Constantinides.

In the field of FPGA arithmetic designs, bit-parallel and bit-serial binary arithmetic are commonly used. Bit-parallel arithmetic generally makes for fast computation, but has a major problem that the more precision of computation we require, the more hardware resource it produces. Compared with bit-parallel arithmetic, serial arithmetic is able to reduce the resource consumption, but is considered to be inappropriate for high-performance application on FPG As because of a significant throughout reduction. Since hardware resource is limited on FPG As, bit serial binary arithmetic shows the potential for high-precision computation. Online arithmetic, a typical bit serial arithmetic approach, can generate results in a most-significant-digit-first fashion, which suggests computation time scales with precision. Basically, the computation can terminate whenever its answer is accurate enough or run out of time. However, classic online arithmetic implemented in digit-serial multiplication or division still scales with precision requirements (a fixed pre-defined precision). Another concern in FPGA arithmetic designs is to compute an iterative algorithm, for instance, we cannot start a new iteration computation until results of previous iterations are obtained. To resolve the constraints above, we aim to construct a class of optimised online arithmetic operators with constant hardware resource to produce results to the arbitrary precision after the arbitrary iteration.

This talk is part of the CAS Talks series.

Tell a friend about this talk:

This talk is included in these lists:

Note that ex-directory lists are not shown.

 

Changes to Talks@imperial | Privacy and Publicity