Imperial College London > Talks@ee.imperial > CAS Talks > fpgaConvNet: Automated Design Space Exploration for FPGA-based Convolutional Neural Networks
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fpgaConvNet: Automated Design Space Exploration for FPGA-based Convolutional Neural NetworksAdd to your list(s) Download to your calendar using vCal
If you have a question about this talk, please contact George A Constantinides. In recent years, Convolutional Neural Networks (ConvNets) have become the state-of-the-art in several Artificial Intelligence tasks. Across the range of applications, the performance needs vary significantly, from high-throughput image recognition to the very low-latency requirements of autonomous cars. In this context, FPG As can provide a potential platform that can be optimally configured based on the different performance needs. However, the complexity of ConvNet models keeps increasing leading to a large design space. This work presents fpgaConvNet, an end-to-end framework for the automatic generation of efficient FPGA -based ConvNet accelerators. The proposed framework employs an automated design methodology based on the Synchronous Dataflow (SDF) paradigm in order to efficiently explore the large design space and target both high-throughput and low-latency applications. Overall our framework yields designs that improve the performance density and the performance efficiency by up to 6× and 4.49× respectively over existing highly-optimised FPGA , DSP and embedded GPU work. This talk is part of the CAS Talks series. This talk is included in these lists:
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