Imperial College London > Talks@ee.imperial > Featured talks > Performance and Enhancement of Programmable Logic Architectures

Performance and Enhancement of Programmable Logic Architectures

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If you have a question about this talk, please contact Professor Peter Cheung.

The excitement and creativity in the field of computing has been enable by the exponential progress of the underlying circuit fabrication technology. Despite this, it is rare that researchers (or industry) create their own chips because it is simply too difficult and expensive, but rather use programmable pre-fabricated instruction set processors.

The other widely-used way of leveraging the underlying technology, chip fabrication is to employ Field-Programmable Gate Arrays (FPGAs) which are made of fine-grained units of logic and memory that can programmably interconnected at the electrical level.

FPG As and instruction processors are capable of implementing similar things, but each has different strengths as measured by cost, speed, energy consumption and ease of use.

In this talk, I will present the results of several research projects that compare FPGA cost, performance and power consumption against these other implementation ‘media’:

1. Hard, fully-fabricated integrated chips (as a reference point).
2. High-performance uniprocessors.
3. General-Purpose Graphics Processing Units (GP GPUs).
4. Soft Processors - processors built on FPGA fabrics.

I will then describe how this informs our work on enhancing the architecture of FPG As, and the infrastructure we are building to enable advanced architecture exploration. This involves a new language to describe more complex structures on an FPGA , and a new, higher-level architecture exploration compiler flow. Our hope is to enable exploration of architectures that can significantly improve energy consumption per function performed.

About the Speaker =========== Jonathan Rose is a Professor in the Edward S. Rogers Sr. Department of Electrical and Computer Engineering at the University of Toronto. He worked as a Post-Doctoral Scholar and then Research Associate at Stanford University, and as a Senior Research Scientist at Xilinx working on the Virtex FPGA . He co-founded Right Track CAD Corporation and was President and CEO of Right Track until it was purchased by Altera, and became part of the Altera Toronto Technology Centre, where Rose was Senior Director until April 30, 2003. His group at Altera Toronto shared responsibility for the development of the architecture for the Altera Stratix, Stratix II, Stratix GX and Cyclone FPG As and associated software. He is the co-founder of the ACM FPGA Symposium, and served as Chair of the Edward S. Rogers Sr. Department of Electrical and Computer Engineering from January 2004 through June 2009. He is a Senior Fellow of Massey College in the University of Toronto, a Fellow of the IEEE , a Fellow of the ACM , and a Fellow of the Canadian Academy of Engineering. His research covers all aspects of FPG As including their architecture, Computer-Aided Design (CAD), Field-Programmable Systems, Soft Processors, and graphics, vision and bio-informatic applications of programmable hardware.

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