Floorplanning for Partial Reconfiguration in FPGAs

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• Pritha Banerjee, ACMU, Indian Statistical Institute, Kolkata, India
• Friday 01 May 2009, 15:00-16:00
• Level 9 Conference Room.

If you have a question about this talk, please contact Dr Christos Bouganis.

Modern Field Programmable Gate Arrays (FPGA) support partial reconfiguration which helps better utilization of heterogeneous resources, such as CLB , RAM, MULs on the FPGA chip by executing parts of application as and when required. In order to take the full advantage of partial reconfigurability, a good scheduling of tasks together with resource aware floorplanning is required such that partial reconfiguration overhead as well as the total wirelength of the floorplans for all the tasks are minimized. We have proposed a global floorplan topology generation and sizing method such that the common modules of a given schedule are placed at fixed positions on the chip throughout, thereby minimizing the partial reconfiguration overhead. The rest of the modules are placed in the remaining area such that the resource requirements of all modules are satisfied while optimizing the wirelength over all tasks. Our experimental results on a set of benchmarks show that our method is fast and yet produces high quality solutions with minimal increase in total wirelength compared to the case when individual tasks are optimally floorplanned disregarding the other tasks of the schedule. In particular, over the nine benchmarks, the average increase in wirelength is 28%, while the time taken to generate the global floorplans for all instances is 1.27x of the total time taken for floorplanning for each task individually.

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