Zero Overhead FPGA Instrumentation

Add to your list(s) Download to your calendar using vCal

• Eddie Hung (Imperial College)
• Tuesday 04 March 2014, 12:00-13:00
• Level 11 Control Seminar room, room 1109a, EE Dept..

If you have a question about this talk, please contact Grigorios Mingas.

FPGA technology is increasingly used to prototype large, complex digital designs for which software simulation is too slow. However, when this prototype doesn’t behave as expected, it is important to understand what the circuit was doing before it failed—- and to do so requires designers to be able to observe nodes inside the FPGA .

In this talk, I will present ways of harnessing the reconfigurable and prefabricated nature of FPG As as a debugging platform. In order to observe circuit nodes with zero overhead, debug instruments are inserted into only the spare FPGA resources that were left unused by the application circuit; thus, completely preserving the area and timing of the original design. To overcome the lack of flexibility presented by using only left-over resources, I will discuss two CAD techniques: first, by building a virtual overlay network that can allow circuit signals to be rapidly multiplexed between a limited set of debug instruments, and secondly, how max-flow techniques can be used to achieve optimal debug visibility.

In addition, I will also cover recent progress on realizing some of these techniques on Xilinx silicon, and in particular, on how I’ve been able to replace the closed-source Xilinx toolchain with the open-source academic equivalent, VPR .

This talk is part of the CAS Talks series.

This talk is included in these lists:

• Andrea Picciau's list
• CAS Talks
• Circuits and Systems Group: Internal Seminars
• Level 11 Control Seminar room, room 1109a, EE Dept.

Note that ex-directory lists are not shown.