FPT practice talk – Exploiting Stochastic Delay Variability on FPGAs with Adaptive Partial Rerouting

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• Justin Wong (Imperial College London)
• Friday 29 November 2013, 14:00-15:00
• Room 610B, EEE Department.

If you have a question about this talk, please contact Grigorios Mingas.

Aggressive transistor scaling will soon lead us to the physical upper-bound of process technology, where stochastic process variability dominates the timing performance of FPGA components. In this paper, a variation-aware partial-rerouting method is proposed to mitigate and take advantage of the effect of delay variability due to process variation. The variation in logic delay across each FPGA (variation map) is measured on commercial FPG As and is used to assess the effectiveness and potential gain of the proposed method on current FPGA architectures. Our partial-rerouting method achieved 5.25% improvement in critical path delay under a delay variability of sigma/mu = 0.3, and is considerably less time consuming than using variation-aware full chipwise routing, which gave a slightly better timing gain of 6.41% but requires 8x more execution time when optimising for 100 target FPG As with unique variation maps.

This talk is part of the CAS Talks series.

This talk is included in these lists:

• Andrea Picciau's list
• CAS Talks
• Circuits and Systems Group: Internal Seminars
• Room 610B, EEE Department

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