Imperial College London > Talks@ee.imperial > CAS Talks > Balancing Higher-Order Convergence and Architectural Efficiency for Finite-Difference Methods

Balancing Higher-Order Convergence and Architectural Efficiency for Finite-Difference Methods

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This research aims to design novel algorithms and hardware architectural acceleration schemes in the implementation of finite difference methods (FDM) with particular focus on higher order convergence. High performance computing has evolved over the last 10 years. Previously faster computations were directly correlated with increasing CPU clock speeds, however, with the recent decline of Moore’s Law, increased performance now scales with parallelism supported by these multi-core devices. With increasing transistor density and performance of these available multi-core architectures, the design of algorithms to schedule parallelism based on the underlying architecture is significant in order to fully utilize the available resources. This initial study has looked at the trinomial-explicit finite difference model, applied to option pricing in financial modeling. Numerous architectural models were tested on an AMD Radeon HD6350 GPU core to explore and compare the performance differences inherent in the different hardware structures. Initial results have shown faster computations with varying architectural models, data showing the extent of distribution error and non-linearity errors relating to the discrete nodes on the lattice have also been obtained. Following from these works, an adaptive mesh model will be investigated. Particularly, novelty will be sought in the development of a dynamically updated adaptive mesh model with a view to advancing the model into a multi-dimensional adaptive solver.

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