Exploiting Algorithm-based Fault Tolerance for Reliability in Parallel Accelerators

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• James Davis (Imperial College)
• Wednesday 29 May 2013, 11:00-12:00
• Level 9 Mahanakorn Lab., EE Dept..

If you have a question about this talk, please contact Grigorios Mingas.

This talk will serve as a summary of my recent work on leveraging low-overhead, algorithm-level error detection for the purposes of fault detection, location and avoidance/correction. The current benchmark application, a parameterisable matrix multiplication accelerator running on the Xilinx Zynq platform, will be presented, followed by an explanation of the adopted error detection scheme. Hardware modifications to support both error detection and runtime algorithm modification will be explained, with exploration into the overheads and potential gains of several candidate correction strategies.

This talk is part of the CAS Talks series.

This talk is included in these lists:

• Andrea Picciau's list
• CAS Talks
• Circuits and Systems Group: Internal Seminars
• Level 9 Mahanakorn Lab., EE Dept.

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