Accelerating the training process of Random Forest classifier on FPGA

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• Chuan Cheng (Imperial College London)
• Wednesday 01 May 2013, 11:00-12:00
• Level 9 Mahanakorn Lab., EE Dept..

If you have a question about this talk, please contact Grigorios Mingas.

In a Random Forest classification problem, the training process becomes the bottleneck of the system when the predicting model needs to be updated periodically. In this talk an FPGA architecture that accelerates the training process will be introduced. We exploit the key features of FPGA devices by combing a fine-grain data-flow processing at low-level and exploiting parallelism at high level. The preliminary results obtained from the simulation of the core is promising, a minimum speedup of 142x is achieved based on the case study of VOC2007 classification problems.

This talk is part of the CAS Talks series.

This talk is included in these lists:

• Andrea Picciau's list
• CAS Talks
• Circuits and Systems Group: Internal Seminars
• Level 9 Mahanakorn Lab., EE Dept.

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