Imperial College London > Talks@ee.imperial > CAS Talks > Classification of variation maps: An efficient technique to combat process variation in FPGAs

Classification of variation maps: An efficient technique to combat process variation in FPGAs

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Technology scaling causes increasing and unavoidable delay variability in FPG As. This paper describes an approach to reduce the delay of the critical path in a design by applying variation aware placement. A full-chipwise placement is realized through Versatile Placement and Routing tools (VPR) modification to achieve 4.84% improvement on average. By using variation maps measured from 129 Altera Cyclone III FPG As (DE0 boards), we demonstrate how spatially correlated variation patterns can be divided into clusters and how the cluster-based method can be used to reduce overall run-time in variation-aware placement and routing (P&R) for FPG As while maintaining good timing improvements 2.85% comparable to full-chipwise P&R.

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