Accelerating the dot-product operation using Field Programmable Gate Arrays

Add to your list(s) Download to your calendar using vCal

• Antonio Roldao Lopes (PhD at IC)
• Thursday 01 October 2009, 12:00-13:00
• Room 611, EEE.

If you have a question about this talk, please contact George A Constantinides.

Dot-products are recurrent operations in scientific computing. The acceleration of these operations is very well suited for Field Programmable Gate Arrays (FPGAs) since these devices can be configured to explore wide parallelism, deep pipelining and deploy highly efficient data-paths. In this presentation it is introduced a dot-product implementation which operates using a hybrid floating-point (FP) and fixed-point (FX) number system. This design receives floating point inputs, and generates a floating point output. Internally it makes use of configurable word-length fixed point number system.

Results using a high-end Xilinx FPGA and an order 150 dot-product demonstrate that, at the price of a small solution accuracy, it is possible to utilize 13 times less resources, operate at a 42% faster clock rate, and achieve a significant reduction in latency when compared to a floating point based dot-product.

Combining these results and utilizing the spare resources, to instantiate more units in parallel, it is possible to achieve an overall speed-up of at least 18 times.

This talk is part of the CAS Talks series.

This talk is included in these lists:

• Andrea Picciau's list
• CAS Talks
• Circuits and Systems Group: Internal Seminars
• Room 611, EEE

Note that ex-directory lists are not shown.