Area Estimation and Optimisation of FPGA Routing Fabrics

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• Alastair Smith (Imperial College London)
• Wednesday 19 August 2009, 09:00-10:00
• Level 9 Mahanakorn Lab., EE Dept..

If you have a question about this talk, please contact George A Constantinides.

This talk is a preview of the talk I will be giving at the FPL conference in Prague later this month.

The majority of the area consumed by an FPGA is due to resources used to route signals between functional units. This talk will focus on how routing resource area can be expressed in a form amenable to Geometric Programming – a form of convex optimisation. These methods have been used to improve FPGA area efficiency, as well as speed up the architecture exploration process.

This talk is part of the CAS Talks series.

This talk is included in these lists:

• Andrea Picciau's list
• CAS Talks
• Circuits and Systems Group: Internal Seminars
• Level 9 Mahanakorn Lab., EE Dept.

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