FPGA implementation of Viola&Jones face detector with dynamic workload balancing

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• Chuan Cheng (Imperial College London)
• Tuesday 26 July 2011, 10:00-11:00
• Room 503/EEE.

If you have a question about this talk, please contact Grigorios Mingas.

The hardware architecture of our proposed FPGA based Viola&Jones face detector will be introduced in detail. The performance of the system has been measured and will be reported. A discussion on the performance and further improvement will be given.

This talk is part of the CAS Talks series.

This talk is included in these lists:

• Andrea Picciau's list
• CAS Talks
• Circuits and Systems Group: Internal Seminars
• Room 503/EEE

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