Efficient FPGA Mapping of Gilbert's Algorithm for SVM Training on Large-Scale Classification Problems

Add to your list(s) Download to your calendar using vCal

• Markos Papadonikolakis (Imperial College)
• Thursday 31 July 2008, 11:30-12:30
• Level 9 Mahanakorn Lab., EE Dept..

If you have a question about this talk, please contact George A Constantinides.

Support Vector Machines (SVMs) are an effective, adaptable and widely used method for supervised classification. However, training an SVM classifier on large-scale problems is proven to be a very time-consuming task for software implementations. This paper presents a scalable high performance FPGA architecture of Gilbert’s Algorithm on SVM , which maximally utilizes the features of an FPGA device to accelerate the SVM training task for large-scale problems. Initial comparisons of the proposed architecture to the software approach of the algorithm show a speed-up factor range of three orders of magnitude for the SVM training time, regarding a wide range of data’s characteristics.

This talk is part of the CAS Talks series.

This talk is included in these lists:

• Andrea Picciau's list
• CAS Talks
• Circuits and Systems Group: Internal Seminars
• Level 9 Mahanakorn Lab., EE Dept.

Note that ex-directory lists are not shown.