Investigating I/O and Memory Bandwidth trade-offs for Iterative Algorithms

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• David Boland, Imperial College London
• Thursday 03 July 2008, 12:00-13:00
• Level 9 Mahanakorn Lab., EE Dept..

If you have a question about this talk, please contact George A Constantinides.

Previous FPGA implementations of iterative algorithms, such as the conjugate gradient and minimum residual algorithm, have focused either on maximum performance or maximum scalability. The designs for maximum performance have been based upon fully utilizing the memory bandwidth on an FPGA , however as the available memory is limited, such a scheme is only possible for small matrix orders. The designs for maximum scalability use external RAM to store the matrices and intermediate results, however this means the input data speed is determined by the I/O bandwidth and results in a dramatically lower performance. This presentation analyses theoretically how it would be possible to trade these factors to achieve an optimum performance for any given matrix order, and briefly examines ways in which to improve the results.

This talk is part of the CAS Talks series.

This talk is included in these lists:

• Andrea Picciau's list
• CAS Talks
• Circuits and Systems Group: Internal Seminars
• Level 9 Mahanakorn Lab., EE Dept.

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