A Unified Data Parallel Programming Model for Multicore Processors, GPUs and FPGA Circuits

Add to your list(s) Download to your calendar using vCal

• Satnam Singh (Microsoft Research Cambridge)
• Thursday 11 March 2010, 12:00-13:00
• Dennis Gabor Seminar Room 611, EE Dept..

If you have a question about this talk, please contact George A Constantinides.

This presentation introduces an embedded domain specific language (DSL) called Accelerator for data-parallel programming which can target GPUs, SIMD instructions on x64 multicore processors and FPGA circuits. This system is implemented as a library of data-parallel arrays and data-parallel operations with implementations in C++ and for .NET languages like C#, VB.NET and F#. We show how a carefully selected set of constraints allow us to generate efficient code or circuits for very different kinds of targets. Finally we compare our approach which is based on JIT -ing with other techniques e.g. CUDA which is an off-line approach as well as to stencil computations. The ability to compile the same data parallel description at an appropriate level of abstraction to different computational elements brings us one step closer to finding models of computation for heterogonous multicore systems. The Accelerator system can be downloaded from http://connect.microsoft.com/acceleratorv2 and the FPGA target will follow as a separate download.

This talk is part of the Featured talks series.

This talk is included in these lists:

• Andrea Picciau's list
• CAS Talks
• COMMSP & CP list
• COMMSP Seminar
• Circuits and Systems Group: Internal Seminars
• Dennis Gabor Seminar Room 611, EE Dept.
• Featured talks
• SAP Talks

Note that ex-directory lists are not shown.