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Circuits and Systems Group: Internal Seminars

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Description to be confirmed

5 upcoming talks and 573 talks in the archive.

Title to be confirmed

User Quentin Corradi (Imperial College).

House Department of Electrical and Electronic Engineering, Room 909B.

Monday 15 April 2024, 13:00-14:00

TAPA: Fast, High-Frequency, Expressive Dataflow HLS Framework

User Jason Cong (UCLA).

House EEE Room 611.

Wednesday 27 March 2024, 16:00-17:00

Efficient Computing In-memory Architectures for FPGA-based Deep Learning Acceleration

User Yuzong Chen (Cornell Tech).

House https://utoronto.zoom.us/j/82613229697.

Tuesday 26 March 2024, 13:00-14:00

Customized computing and machine learning

User Atefeh Sohrabizadeh (UCLA).

House Department of Electrical and Electronic Engineering, Room 909B.

Monday 25 March 2024, 13:00-14:00

AutoWS: Automate Weights Streaming in Layer-wise Pipelined DNN Accelerators

User Zhewen Yu (Imperial College).

House Department of Electrical and Electronic Engineering, Room 909B.

Monday 18 March 2024, 13:00-14:00

Memory-aware dynamic spatially adaptive inference

User Giorgos Zampokas.

House Department of Electrical and Electronic Engineering, Room 909B.

Monday 11 March 2024, 13:00-14:00

FPGA IMPLEMENTATION OF A TIME SERIES FORECASTING NETWORK USING BLOCK MINIFLOAT ARITHMETIC

User Wenjie Zhou (University of Sydney).

House https://utoronto.zoom.us/j/82613229697.

Tuesday 27 February 2024, 14:00-15:00

Datapath Power Optimization: A Rewriting Approach

User Sam Coward (Imperial College).

House Department of Electrical and Electronic Engineering, Room 909B.

Monday 19 February 2024, 13:00-14:00

SMOF: Streaming Modern CNNs on FPGAs with Smart Off-Chip Eviction

User Petros Toupas (Imperial College).

House Department of Electrical and Electronic Engineering, Room 909B.

Monday 12 February 2024, 13:00-14:00

MX for FPGA

User Ebby Samson (Imperial College).

House Department of Electrical and Electronic Engineering, Room 909B.

Monday 05 February 2024, 13:00-14:00

Deep Learning Acceleration on Current and Future Reconfigurable Architectures

User Andrew Boutros (University of Toronto).

House Department of Electrical and Electronic Engineering, Room 909B.

Thursday 01 February 2024, 15:30-16:30

High Performance FPGA Design

User Martin Langhammer (Intel and Imperial).

House Department of Electrical and Electronic Engineering, Room 909B.

Monday 29 January 2024, 13:00-14:00

A Review on Custom Accelerators for Transformer Inference

User Keran Zheng (Imperial College).

House Room 503, EEE.

Monday 22 January 2024, 13:00-14:00

Implementing and synthesizing math function implementations

User Pavel Panchekha (University of Utah).

House Department of Electrical and Electronic Engineering, Room 909B.

Thursday 18 January 2024, 11:00-12:00

Challenges and Solutions in Low-Precision Training Methods

User Taowen (Tony) Liu (Imperial College).

House Department of Electrical and Electronic Engineering, Room 909B.

Monday 11 December 2023, 13:00-14:00

Bit-Level Manipulated Graph Neural Networks

User Pedro Gimenes (Imperial College).

House Department of Electrical and Electronic Engineering, Room 909B.

Monday 04 December 2023, 13:00-14:00

PolyLUT: Learning Piecewise Polynomials for Ultra-Low Latency FPGA LUT-based Inference

User Marta Andronic (Imperial College).

House Room 503, EEE.

Wednesday 29 November 2023, 12:30-13:00

eGPU: A 750 MHz Class Soft GPGPU for FPGA

User Martin Langhammer (Intel and Imperial).

House Department of Electrical and Electronic Engineering, Room 909B.

Monday 27 November 2023, 13:00-14:00

Recipe for Sub-8-bit LLMs

User Cheng Zhang (Imperial College).

House Department of Electrical and Electronic Engineering, Room 909B.

Monday 20 November 2023, 13:00-14:00

A primer on stochastic computing and its challenges

User Julie Hsiao (University of Toronto).

House Department of Electrical and Electronic Engineering, Room 909B.

Monday 20 November 2023, 10:00-11:00

A Framework for Designing Gaussian Belief Propagation Accelerators for use in SLAM Problems

User Omar Sharif (Imperial College).

House Department of Electrical and Electronic Engineering, Room 909B.

Monday 13 November 2023, 13:00-14:00

ATHEENA Gets Buff(er)ed: Modelling and Constructing Early-Exit Network FPGA Accelerators

User Benjamin Biggs (Imperial College).

House Department of Electrical and Electronic Engineering, Room 909B.

Monday 06 November 2023, 13:00-14:00

From Sparsity to HBM: HPIPE's Advancements in FPGA CNN Acceleration

User Mario Doumet.

House https://utoronto.zoom.us/j/82613229697.

Tuesday 24 October 2023, 14:00-15:00

An exploration of regularisation and pruning techniques, hyperparameter optimisations and lightweight NAS for PolyLUT

User Wendy Li (Imperial College).

House Department of Electrical and Electronic Engineering, Room 909B.

Monday 23 October 2023, 13:00-14:00

Hardware verification^2. Uncovering bugs in Formal Equivalence Checkers using fuzzing.

User Michalis Pardalos (Imperial College).

House Department of Electrical and Electronic Engineering, Room 909B.

Monday 16 October 2023, 13:00-14:00

TPU V4 and Trends in Accelerator Hardware

User Mike Hutton (Google).

House Online - see abstract.

Tuesday 26 September 2023, 14:00-15:00

Window-Based Early-Exit Cascades for Uncertainty Estimation: When Deep Ensembles are More Efficient than Single Models

User Guoxuan Xia (Imperial College).

House Department of Electrical and Electronic Engineering, Room 909B.

Monday 18 September 2023, 13:00-14:00

PolyLUT: Learning Piecewise Polynomials for Ultra-Low Latency FPGA LUT-based Inference

User Marta Andronic (Imperial College).

House Department of Electrical and Electronic Engineering, Room 909B.

Monday 10 July 2023, 13:00-14:00

MLIR - Connecting domain-specific languages to domain-optimized accelerators

User Samuel Bayliss (AMD).

House Department of Electrical and Electronic Engineering, Room 503.

Wednesday 05 July 2023, 16:00-17:00

Mixed-TD: Efficient Neural Network Accelerator with Layer-Specific Tensor Decomposition

User Zhewen Yu (Imperial College).

House Department of Electrical and Electronic Engineering, Room 909B.

Monday 03 July 2023, 13:00-14:00

Designing fast, adaptable machine learning devices at the edge – and verifying they actually work

User David P Boland (U Sydney).

House Department of Electrical and Electronic Engineering, Room 909B.

Tuesday 27 June 2023, 11:00-12:00

Large Model Training at Wafer-Scale

User Kevin E Murray (Cerebras).

House Department of Electrical and Electronic Engineering, Room 611.

Wednesday 21 June 2023, 12:00-13:00

Exploring spatial sparsity for more efficient CNNs in semantic segmentation

User Giorgos Zampokas.

House Department of Electrical and Electronic Engineering, Room 909B.

Monday 19 June 2023, 13:00-14:00

Automating Constraint-Aware Datapath Optimization using E-Graphs

User Sam Coward (Imperial College).

House Department of Electrical and Electronic Engineering, Room 909B.

Monday 12 June 2023, 13:00-14:00

Testing the stability of logic synthesis tools

User Quentin Corradi (Imperial College).

House Department of Electrical and Electronic Engineering, Room 909B.

Monday 05 June 2023, 13:00-14:00

Speculative Loop Pipelining for HLS

Note unusual room

User Steven Derrien, IRISA.

House Department of Electrical and Electronic Engineering, Room 611.

Tuesday 23 May 2023, 11:00-12:00

Secret Sharing: Two Party Fair Exchange

User Alexander Dalton (Imperial College).

House Department of Electrical and Electronic Engineering, Room 909B.

Monday 08 May 2023, 13:00-14:00

HARFLOW3D: A Latency-Oriented 3D-CNN Accelerator Toolflow for HAR on FPGA Devices

User Petros Toupas (Imperial College).

House Department of Electrical and Electronic Engineering, Room 909B.

Tuesday 02 May 2023, 15:00-16:00

The ABC of formal verification

User Ashish Darbari (Axiomise).

House Department of Electrical and Electronic Engineering, Room 909B.

Monday 24 April 2023, 13:00-14:00

ATHEENA: A Toolflow for Hardware Early-Exit Network Automation

User Benjamin Biggs (Imperial College).

House Department of Electrical and Electronic Engineering, Room 909B.

Monday 17 April 2023, 13:00-14:00

My Research in Approximate Circuit Design

User Laura Pozzi (USI / Lugano).

House Department of Electrical and Electronic Engineering, Room 909B.

Monday 06 March 2023, 13:00-14:00

Parallelising Control Flow in Dynamic-Scheduling High-Level Synthesis

User Jianyi Cheng (Imperial College).

House Department of Electrical and Electronic Engineering, Room 909B.

Monday 06 February 2023, 13:00-14:00

Validating the (Memory) Persistency Semantics of Intel-x86 Architecture

User Vasilis Klimis.

House Teams (in the "CAS Seminars" team).

Monday 06 June 2022, 13:00-14:00

Out-of-Distribution Detection for Selective Classification: It's OK to Confuse ID with OOD if the Prediction Will Be Wrong Anyway

User Guoxuan Xia (Imperial College).

House Teams (in the "CAS Seminars" team).

Monday 23 May 2022, 13:00-14:00

HLS in CIRCT: An overview

User Morten Peteresen (External).

House Teams (in the "CAS Seminars" team).

Monday 09 May 2022, 13:00-14:00

Title to be confirmed

User James Davis (Imperial College).

House Teams (in the "CAS Seminars" team).

Monday 28 March 2022, 13:00-14:00

UTILIZING DNN EXPLAINABILITY FOR PRUNING AND QUANTIZATION

User Anna Tzatzopoulou (Imperial College London).

House Teams (in the "CAS Seminars" team).

Monday 14 March 2022, 13:00-14:00

Verified software, verified hardware, verified everything

User Andreas Lööw (Imperial College).

House Teams (in the "CAS Seminars" team).

Monday 07 March 2022, 13:00-14:00

GEORGE - Generating Equivalent and Optimal RTL with Great Ease

User Sam Coward (Imperial College).

House Teams (in the "CAS Seminars" team).

Monday 07 February 2022, 13:00-14:00

Finding and Finessing Static Islands in Dynamically Scheduled Circuits

User Jianyi Cheng (Imperial College).

House Teams (in the "CAS Seminars" team).

Monday 31 January 2022, 13:00-14:00

Design and Optimisation of CNN Streaming Architectures

User Alexander Montgomerie-Corcoran (Imperial College).

House Teams (in the "CAS Seminars" team).

Monday 24 January 2022, 16:00-17:00

Exploiting spatial sparsity for more efficient CNNs

User Giorgos Zampokas.

House Teams (in the "CAS Seminars" team).

Monday 17 January 2022, 16:00-17:00

Homomorphic Encryption for CNNs

User Ben Chua (Imperial College).

House Teams (in the "CAS Seminars" team).

Monday 13 December 2021, 16:00-17:00

Mutual Information Driven Approximate Synthesis

User Sina Boroumand (Imperial College).

House Teams (in the "CAS Seminars" team).

Monday 06 December 2021, 16:00-17:00

DiSCuS: Distributed Homomorphic Encryption on Edge Devices

User Alexander Dalton (Imperial College).

House Teams (in the "CAS Seminars" team).

Monday 29 November 2021, 16:00-17:00

Hyperblock Scheduling for a Verified High-Level Synthesis Tool

User Yann Herklotz Grave ( Imperial College).

House Teams (in the "CAS Seminars" team).

Monday 22 November 2021, 16:00-17:00

Introduction to CXL

User Dan Iorga (Imperial College).

House Teams (in the "CAS Seminars" team).

Monday 15 November 2021, 16:00-17:00

Title to be confirmed

User Diederik Vink (Imperial College).

House Teams (in the "CAS Seminars" team).

Monday 08 November 2021, 16:00-17:00

Resource Sharing for Verified High-Level Synthesis

User Michalis Pardalos.

House Teams (in the "CAS Seminars" team).

Monday 01 November 2021, 16:00-17:00

Low-Cost On-device Partial Domain Adaptation (LoCO-PDA) : Enabling Efficient CNN Retraining on Edge Devices

User Aditya Rajagopal.

House Teams (in the "CAS Seminars" team).

Monday 18 October 2021, 16:00-17:00

Towards the acceleration of 3D-CNNs for efficient Human Action Recognition

User Petros Toupas.

House Teams (in the "CAS Seminars" team).

Monday 11 October 2021, 16:00-17:00

StreamSVD: Low-rank Approximation and Streaming Accelerator Co-design

User Zhewen Yu.

House Teams (in the "CAS Seminars" team).

Monday 04 October 2021, 16:00-17:00

Egg: Efficient Equality Saturation for Rewriting Expressions

User Sam Coward (Imperial College).

House Teams (in the "CAS Seminars" team).

Monday 12 July 2021, 16:00-17:00

Enabling Binary Neural Network Training on the Edge

User Erwei Wang (Imperial College).

House Teams (in the "CAS Seminars" team).

Monday 28 June 2021, 16:00-17:00

Input-dependent computation in Neural Networks (Hardware Acceleration of Early-Exit Networks)

User Benjamin Biggs (Imperial College).

House Teams (in the "CAS Seminars" team).

Monday 21 June 2021, 16:00-17:00

Custom-Precision Mathematical Library Explorations for Code Profiling and Optimization

User Matei Istoan (University of Versailles).

House Teams (in the "CAS Seminars" team).

Monday 07 June 2021, 16:00-17:00

Talk Postponed

User George A Constantinides (Imperial College).

House Teams (in the "CAS Seminars" team).

Monday 24 May 2021, 16:00-17:00

Rapid RTL Prototyping (for Fun and Profit)

User James Davis (Imperial College).

House Teams (in the "CAS Seminars" team).

Monday 17 May 2021, 16:00-17:00

Probabilistic Scheduling in High-Level Synthesis

User Jianyi Cheng (Imperial College).

House Teams (in the "CAS Seminars" team).

Monday 26 April 2021, 16:00-17:00

Addressing DRAM Power Consumption in CNN Accelerators

User Alexander Montgomerie-Corcoran (Imperial College).

House Teams (in the "CAS Seminars" team).

Monday 15 March 2021, 16:00-17:00

Towards more efficient stereo matching with CNNs

User Giorgos Zampokas.

House Teams (in the "CAS Seminars" team).

Monday 08 March 2021, 16:00-17:00

On the Nature of Manual RTL Optimisations

User Theo Drane (Intel).

Monday 22 February 2021, 16:00-17:00

Introduction to Homomorphic Encryption and Its Applications

User Ben Chua.

Monday 08 February 2021, 16:00-17:00

Title to be confirmed

User Jonathan R Beaumont (Imperial College).

Monday 01 February 2021, 16:00-17:00

Approximate Logic Synthesis from Examples

User Sina Boroumand (Imperial College).

Monday 25 January 2021, 16:00-17:00

Hardware Design and Verification with Cava

User Satnam Singh (Google Research).

House Teams (in the "CAS Seminars" team).

Wednesday 20 January 2021, 16:00-17:00

Report from Internship at Samsung

User Alexandros Kouris (Imperial College).

Monday 18 January 2021, 16:00-17:00

Boolean Analysis

User George A Constantinides (Imperial College).

Monday 18 January 2021, 10:00-11:00

Title to be confirmed

User Jiyu Fang (Imperial College).

Monday 11 January 2021, 16:00-17:00

Homomorphic Encryption on Resource Constrained Devices

User Alex Dalton.

Monday 14 December 2020, 16:00-17:00

Formal Verification of High-Level Synthesis

User Yann Herklotz Grave ( Imperial College).

Monday 07 December 2020, 16:00-17:00

Constructing non-linear Random Number Generators from iterated linear mappings

User David B Thomas (Imperial College).

Monday 30 November 2020, 16:00-17:00

The Semantics of Shared Memory in CPU/FPGA Systems

User Dan Iorga (Imperial College).

Monday 23 November 2020, 16:00-17:00

Sparse and efficient deep neural network optimisation for embedded intelligence

User Jia Bi (Southampton).

Monday 02 November 2020, 16:00-17:00

Now that I can predict, I can adapt: Towards CNN adaptation of Edge GPUs through modelling of the training process

User Aditya Rajagopal.

Monday 19 October 2020, 16:00-17:00

Memory Optimized Convolution Hardware Accelerator for Training (MOCHA-T)

User Diederik Vink (Imperial College).

Monday 12 October 2020, 16:00-17:00

Spiking Neural Network Implementation on Distributed Reconfigurable Cluster Architecture

User Shahsavari, Mahyar .

Monday 05 October 2020, 16:00-17:00

Rethinking BNN Inference and Training on Embedded FPGAs

User Erwei Wang (Imperial College).

Tuesday 01 September 2020, 16:00-17:00

Precise pointer analysis in high-level synthesis

User Nadesh Ramanathan.

Monday 10 August 2020, 16:00-17:00

Semiconductor Startups 2020, Back to the Future

User Pete Rodriguez, CEO, Silicon Catalyst.

Thursday 11 June 2020, 17:00-18:00

Predictable Accelerator Design with Time-Sensitive Affine Types

User Rachit Nigam (Cornell).

Monday 08 June 2020, 16:00-17:00

Training Convolutional Neural Networks using Xilinx AI Engines

User Erwei Wang (Imperial College).

House Level 9 Seminar Room, EEE Dept..

Monday 27 April 2020, 16:00-17:00

Slow and Steady: Measuring and Tuning Multicore Interference

Practice Talk for RTAS

User Dan Iorga.

House Level 9 Seminar Room, EEE Dept..

Monday 06 April 2020, 16:00-17:00

Efficient Video Recognition on Resource Constrained Mobile Devices

User Amin Sabet (University of Southampton).

House Level 9 Seminar Room, EEE Dept..

Thursday 13 February 2020, 10:00-11:00

Combining Dynamic & Static Scheduling in High-level Synthesis

User Jianyi Cheng (Imperial College).

House Level 9 Seminar Room, EEE Dept..

Monday 10 February 2020, 16:00-17:00

Finding and Understanding Bugs in FPGA Synthesis Tools

FPGA Practice Talk

User Yann Herklotz (Imperial College).

House Level 9 Seminar Room, EEE Dept..

Monday 03 February 2020, 16:00-17:00

Synchronous vs Asynchronous on POETS

User Jonathan R Beaumont (Imperial College).

House Level 9 Seminar Room, EEE Dept..

Monday 27 January 2020, 16:00-17:00

Tcling Quartus

User James Davis (Imperial College).

House Level 9 Seminar Room, EEE Dept..

Monday 20 January 2020, 16:00-17:00

Combining Dynamic & Static Scheduling in High-level Synthesis

User Jianyi Cheng (Imperial College).

House Level 9 Seminar Room, EEE Dept..

Monday 13 January 2020, 16:00-17:00

Global analysis of C Concurrency in High-level Synthesis

User Nadesh Ramanathan (Imperial College).

House Level 9 Seminar Room, EEE Dept..

Monday 09 December 2019, 16:00-17:00

Modeling Round-Off Error in the Fast Gradient Method for Predictive Control

User Ian McInerney (Imperial College).

House Level 9 Seminar Room, EEE Dept..

Monday 02 December 2019, 16:30-17:30

Analysis Methods for Memory in High-Level Synthesis

User George A Constantinides (Imperial College).

House Level 9 Seminar Room, EEE Dept..

Monday 02 December 2019, 16:00-16:30

Approximate Circuit Design Using Information Theory

User Sina Boroumand (Imperial College).

House Level 9 Seminar Room, EEE Dept..

Monday 25 November 2019, 16:00-17:00

Synthesis Without State Explosion -- from concurrent processes to netlists

User Dennis Fury (Plumstead Publishing).

House Level 9 Seminar Room, EEE Dept..

Monday 18 November 2019, 16:00-17:00

A probabilistic programming approach to the accuracy and stability of numerical algorithms

User Fredrik Dahlqvist.

House Level 9 Seminar Room, EEE Dept..

Monday 21 October 2019, 17:00-18:00

Informed Region Selection for Efficient UAV-based Vehicle Detection on Embedded GPUs

User Alexandros Kouris (Imperial College).

House Level 9 Seminar Room, EEE Dept..

Monday 21 October 2019, 16:00-17:00

CANCELLED: Approximate Circuit Design Using Information Theory

User Sina Boroumand (Imperial College).

House Level 9 Seminar Room, EEE Dept..

Monday 14 October 2019, 16:00-17:00

Formalising isolation levels in SQL database transactions (tentative title)

User Michail Pardalos, Imperial College London.

House Level 9 Seminar Room, EEE Dept..

Monday 07 October 2019, 16:00-17:00

Energy Efficient VLSI Circuits for Machine Learning On-chip

User Hao Yu (Southern University of Science and Technology, China).

House Level 9 Seminar Room, EEE Dept..

Monday 30 September 2019, 16:00-17:00

Understanding memory consistency in CPU+FPGA devices

User Dan Iorga (Imperial).

House EEE Room 611.

Monday 29 July 2019, 16:00-17:00

Fuzzing Verilog

User Yann Herklotz Grave, Imperial College.

House Level 9 Seminar Room, EEE Dept..

Monday 01 July 2019, 16:00-17:00

Tuning Network Topology - existing works, and future directions

User Aditya Rajagopal.

House Level 9 Seminar Room, EEE Dept..

Monday 24 June 2019, 16:00-17:00

The state-of-the-art in meta-learning and hyper-parameter optimization

User Diederik Vink (Imperial College).

House Level 9 Seminar Room, EEE Dept..

Monday 17 June 2019, 16:00-17:00

Report back from FCCM 2019

User Erwei Wang (Imperial College).

House Level 9 Seminar Room, EEE Dept..

Monday 10 June 2019, 16:00-17:00

Dissipative Particle Dynamics using POETS technology

User Jonathan R Beaumont (Imperial College).

House Level 9 Seminar Room, EEE Dept..

Monday 03 June 2019, 16:00-17:00

Rethinking Deep Learning: Architectures and Algorithms

User George A Constantinides (Imperial College).

House Level 9 Seminar Room, EEE Dept..

Monday 20 May 2019, 16:00-17:00

CANCELLED: Learn Boolean Network using SAT to Design Approximate Circuits

User Sina Boroumand (Imperial College).

House Level 9 Seminar Room, EEE Dept..

Monday 13 May 2019, 16:00-17:00

Report on FPGA 2019

User Jianyi Cheng.

House Level 9 Seminar Room, EEE Dept..

Monday 29 April 2019, 16:00-17:00

[FCCM'19 practice talk] LUTNet: Rethinking Inference in FPGA Soft Logic

Note unusual date

User Erwei Wang (Imperial College).

House Level 9 Seminar Room, EEE Dept..

Thursday 25 April 2019, 16:00-17:00

[FCCM'19 practice talk] LUTNet: Rethinking Inference in FPGA Soft Logic

User Erwei Wang (Imperial College).

House Level 9 Seminar Room, EEE Dept..

Monday 15 April 2019, 16:00-17:00

CANCELLED: Approximate Arithmetic - A Hardware Perspective

User George A Constantinides (Imperial College).

House Level 9 Seminar Room, EEE Dept..

Monday 01 April 2019, 16:00-17:00

Modulo Scheduling in Electronic System Level Synthesis - Improving Performance and Control

Room changed

User Patrick Sittel (U Kassel, Germany).

House Denis Gabor Seminar Room, 611.

Monday 18 March 2019, 16:00-17:00

Less is more: graph partitioning for approximate circuit design

User Ilaria Scarabottolo (USI Lugano).

House Level 9 Seminar Room, EEE Dept..

Monday 11 March 2019, 16:00-17:00

Semantics of higher-order probabilistic programs

User Fredrik Dahlqvist (Imperial College London).

House Level 9 Seminar Room, EEE Dept..

Monday 04 March 2019, 16:00-17:00

Preserving Privacy through Processing Encrypted Data

User Miriam Leeser (Northeastern University).

House Level 9 Seminar Room, EEE Dept..

Monday 11 February 2019, 16:00-17:00

EASY: Efficient Arbiter SYnthesis from Multi-threaded Code

User Jianyi Cheng (Imperial College).

House Level 9 Seminar Room, EEE Dept..

Monday 04 February 2019, 16:00-17:00

EASY: Efficient Arbiter SYnthesis from Multi-threaded Code

User Jianyi Cheng (Imperial College).

House Level 9 Seminar Room, EEE Dept..

Monday 28 January 2019, 16:00-17:00

No talk this week - no room available

User Speaker to be confirmed.

House Level 9 Seminar Room, EEE Dept..

Monday 21 January 2019, 16:00-17:00

Speeding up HLS: Rational II modulo scheduling

Note unusual time

User Patrick Sittel (visiting student from U Kassel, Germany).

House Denis Gabor Seminar Room, 611.

Wednesday 16 January 2019, 14:00-15:00

Modular SRAM-based Binary Content-Addressable Memories

User Ameer Abdelhadi (Imperial College).

House Level 9 Seminar Room, EEE Dept..

Monday 14 January 2019, 16:00-17:00

Custom precision FPGA and GPU Multiple Precision Training (MuPT) in Caffe

User Diederik Vink (Imperial College).

House Denis Gabor Seminar Room, 611.

Monday 07 January 2019, 16:00-17:00

Multi-precision training for CNNs

User Aditya Rajagopal.

House Level 9 Seminar Room, EEE Dept..

Monday 10 December 2018, 16:00-17:00

Project Trellis: enabling open source tools for the Lattice ECP5 FPGA

User David Shah (Imperial College, Undergraduate).

House Level 9 Seminar Room, EEE Dept.

Monday 03 December 2018, 16:00-17:00

Analysis and Synthesis of Floating-Point Routines

User Zvonimir Rakamaric (University of Utah).

House Denis Gabor Seminar Room, 611.

Tuesday 27 November 2018, 16:00-17:00

What's inside Xilinx's 7nm Versal Adaptive Compute Acceleration Platforms

User Samuel Bayliss (Xilinx).

House Denis Gabor Seminar Room, 611.

Tuesday 27 November 2018, 11:00-12:00

An IP provider’s perspective on functional safety

User Visiting Prof Pete Harrod (Arm).

House Level 9 Seminar Room, EEE Dept..

Monday 26 November 2018, 16:00-17:00

Asynchronous Systems - A world without time, part III

User Jonny Beaumont.

House Level 9 Seminar Room, EEE Dept..

Monday 19 November 2018, 16:00-17:00

Learning to Fly by MySelf: A Self-Supervised CNN-based Approach for Autonomous Navigation

User Alexandros Kouris (Imperial College).

House Level 9 Seminar Room, EEE Dept.

Monday 05 November 2018, 16:00-17:00

The Circuits and Systems Group

User Various.

House Level 9 Seminar Room, EEE Dept.

Tuesday 30 October 2018, 09:30-11:30

Asynchronous Systems - A world without time, part II

User Jonny Beaumont.

House Level 9 Seminar Room, EEE Dept..

Monday 22 October 2018, 16:00-17:00

From Custom CAD Tools to Circuit Reliability to IP Security: FPGA Research at BYU

User Brent Nelson (Brigham Young University).

House Level 9 Seminar Room, EEE Dept.

Monday 15 October 2018, 16:00-17:00

Logic synthesis using SAT-solvers

User Sina Boroumand (Imperial College).

House Level 9 Seminar Room, EEE Dept.

Wednesday 10 October 2018, 16:30-17:30

POSTPONED

Room changed

User Sina Boroumand (Imperial College).

House Meeting room 1, Institute of Biomedical Engineering (IBE).

Monday 08 October 2018, 16:00-17:00

A custom hardware architecture for state of the art Semi-dense mapping

User Konstantinos Boikos (Imperial College).

House Level 9 Seminar Room, EEE Dept..

Monday 01 October 2018, 16:00-17:00

The E-method

User Matei Valentin Istoan (Imperial College).

House Room 610B, EEE Building.

Monday 24 September 2018, 16:00-17:00

Computational Self-awareness for Cross-layer Resilience

User Nikil Dutt (UC Irvine).

House Level 9 Seminar Room, EEE Dept..

Thursday 20 September 2018, 11:00-12:00

Various Arithmetic Talks

User Speaker to be confirmed.

House Level 9 Seminar Room, EEE Dept.

Monday 10 September 2018, 10:30-16:45

Asynchronous Systems - A world without time

User Jonny Beaumont.

House EEE Department, Room 503.

Monday 03 September 2018, 16:00-17:00

What’s happening in programming languages research?

User John Wickerson (Imperial College).

House Level 9 Seminar Room, EEE Dept..

Monday 23 July 2018, 16:00-17:00

Training Position-Aware Top-k ListNet for Ranking Using Fixed-Point Representation

User Qiang Li (Imperial College).

House Level 9 Seminar Room, EEE Dept..

Monday 16 July 2018, 16:00-17:00

Formalizing mathematics and critical systems using the Coq proof assistant

User Florian Faissole.

House Level 9 Seminar Room, EEE Dept..

Monday 16 July 2018, 15:00-16:00

Automated Full-Stack Memory Model Verification with the Check suite

Note unusual date

User Yatin Manerkar (Princeton).

House Level 9 Seminar Room, EEE Dept..

Thursday 12 July 2018, 14:00-15:00

Gate-Level Approximate Computing: How to Carve a Circuit, to Remove the Inessential

User Laura Pozzi (U. Lugano).

House Level 9 Seminar Room, EEE Dept..

Wednesday 11 July 2018, 11:00-12:00

How to Write

User James Davis (Imperial College).

House Level 9 Seminar Room, EEE Dept..

Monday 09 July 2018, 16:00-17:00

LUT-based BNN: Forward Propagation with Arbitrary Binary Operations

User Erwei Wang (Imperial College).

House Level 9 Seminar Room, EEE Dept..

Monday 02 July 2018, 16:00-17:00

f-CNNx: Deploying Multiple CNNs in Complex AI Systems

User Stelios I. Venieris (Imperial College London).

House Level 9 Seminar Room, EEE Dept..

Monday 25 June 2018, 16:00-17:00

Digit Elision for Arbitrary-accuracy Iterative Computation (ARITH Practice Talk)

User He Li, EEED.

House Room 610B, EEE Department.

Wednesday 20 June 2018, 14:00-16:00

CascadeCNN: Pushing the Performance Limits of Quantisation in Convolutional Neural Networks

User Alexandros Kouris (Imperial College).

House Level 9 Seminar Room, EEE Dept..

Monday 18 June 2018, 16:00-17:00

Digit Elision for Arbitrary-accuracy Iterative Computation (ARITH Practice Talk)

User He Li, EEED.

House Level 9 Seminar Room, EEE Dept..

Tuesday 12 June 2018, 15:30-17:00

Digit Elision for Arbitrary-accuracy Iterative Computation (ARITH Practice Talk)

User He Li (Imperial College).

House Level 9 Seminar Room, EE Dept..

Monday 04 June 2018, 16:00-17:00

Injecting many FPGA configuration faults

User Shane Fleming (Imperial College).

House Level 9 Seminar Room, EE Dept..

Monday 14 May 2018, 16:00-17:00

FCCM Practice: Concurrency-Aware Thread Scheduling for High-Level Synthesis

User Nadesh Ramanathan (Imperial College).

House Level 9 Seminar Room, EE Dept..

Monday 16 April 2018, 16:00-17:00

Online Algorithms and the E-Method on FPGAs

User Matei Valentin Istoan (Imperial College).

House Level 9 Seminar Room, EE Dept..

Monday 26 March 2018, 16:00-17:00

Online Algorithms and the E-Method on FPGAs

User Speaker to be confirmed.

House Level 9 Seminar Room, EE Dept..

Monday 26 March 2018, 16:00-17:00

Black-box approximation of bivariate functions

User David B Thomas (Imperial College).

House Level 9 Seminar Room, EE Dept..

Monday 19 February 2018, 16:00-17:00

The state of the art in SLAM and why FPGA-SoCs can play an important role

User Konstantinos Boikos (Imperial College).

House Level 9 Seminar Room, EE Dept..

Monday 29 January 2018, 16:00-17:00

How to prove a theorem using the Isabelle Proof Assistant

User John Wickerson (Imperial College).

House Level 9 Seminar Room, EE Dept..

Monday 22 January 2018, 16:00-17:00

CNN-to-FPGA Toolflows: An Overview and Future Directions

User Stelios I. Venieris (Imperial College London).

House Level 9 Seminar Room, EE Dept..

Monday 15 January 2018, 16:00-17:00

Using the Intel HARP2 System - A Tutorial

User Felix Winterstein (Imperial College).

House Department of Electrical and Electronic Engineering, Room 503.

Thursday 11 January 2018, 11:00-13:00

Acceleration of Top-k ListNet Training Using FPGA

User Qiang (Imperial College).

House Level 9 Seminar Room, EE Dept..

Monday 18 December 2017, 15:00-16:00

ZepAlloc: Three-Stage Hardware Dynamic Memory Manager in FPGA

User Hilda Xue (CAS).

House Level 9 Seminar Room, EE Dept..

Monday 11 December 2017, 15:00-16:00

Reconfigurable Computing at TU Darmstadt: Architectures, Tools, and Applications

User Andreas Koch (TU Darmstadt).

House Level 9 Seminar Room, EE Dept..

Monday 04 December 2017, 15:00-16:00

ARCHITECT: Arbitrary-precision Constant-hardware Iterative Compute

User He LI, CAS Group, Imperial College.

House Department of Electrical and Electronic Engineering, Room 909B.

Friday 01 December 2017, 15:00-16:00

<FPT Practice Talk> ARCHITECT: Arbitrary-precision Constant-hardware Iterative Compute

User He Li (Imperial College).

House Department of Electrical and Electronic Engineering, Room 503.

Tuesday 28 November 2017, 15:00-16:00

Emergent Synchronisation on the POETS Architecture

User Shane Fleming (Imperial College).

House Level 9 Seminar Room, EE Dept..

Monday 20 November 2017, 15:00-16:00

Scaling Up Modulo Scheduling For High-Level Synthesis

User Leandro de Souza Rosa.

House Seminar Room 909b, EEE Building.

Tuesday 14 November 2017, 16:00-17:00

The PRiME Framework: Application- and Platform-agnostic Runtime Management

User James Davis (Imperial College).

House Level 9 Seminar Room, EE Dept..

Monday 13 November 2017, 15:00-16:00

Title to be confirmed

User Konstantinos Boikos (Imperial College).

House Level 9 Seminar Room, EE Dept..

Monday 30 October 2017, 15:00-16:00

Title to be confirmed

User Matei Valentin Istoan (Imperial College).

House Level 9 Seminar Room, EE Dept..

Monday 23 October 2017, 15:00-16:00

A Method for Computing Sine and Cosine on FPGAs

User Matei Valentin Istoan (Imperial College).

House Level 9 Seminar Room, EE Dept..

Monday 23 October 2017, 15:00-16:00

Area-efficient Division for ARbitrary-precision Constant-Hardware ITErative CompuTe

User He Li (Imperial College).

House Level 9 Seminar Room, EE Dept..

Monday 16 October 2017, 15:00-16:00

Compiling OP2 into events, and beyond!!! Maybe...

User David B Thomas (Imperial College).

House Level 9 Seminar Room, EE Dept..

Monday 02 October 2017, 15:00-16:00

Title to be confirmed

User John Wickerson (Imperial College).

House Level 9 Seminar Room, EE Dept..

Monday 25 September 2017, 15:00-16:00

A Framework for Mapping Multiple Convolutional Neural Networks on FPGAs

User Stelios I. Venieris (Imperial College London).

House Level 9 Seminar Room, EE Dept..

Monday 18 September 2017, 15:00-16:00

Scheduling weakly consistency C concurrency for reconfigurable hardware

User Nadesh Ramanathan (Imperial College).

House Level 9 Seminar Room, EE Dept..

Monday 11 September 2017, 15:00-16:00

Redundancy in Neural Network Hardware and A Case Study of Parameter Precision

User Alex Su.

House IBE Meeting Room 1.

Monday 10 July 2017, 15:00-16:00

POETS : partially ordered event triggered systems

User David B Thomas (Imperial College).

House Level 9 Seminar Room, EE Dept..

Monday 03 July 2017, 15:00-16:00

Streaming Abstractions for FPGA High Level Synthesis

User John McAllister (Queen's University Belfast).

House Level 9 Seminar Room, EE Dept..

Monday 03 July 2017, 14:00-15:00

Tile Size Selection for Optimized Memory Reuse in High-Level Synthesis

User Junyi Liu ().

Monday 19 June 2017, 15:00-16:00

Shared Virtual Memory in Heterogeneous Systems

User Felix Winterstein (Imperial College).

House Level 9 Seminar Room, EE Dept..

Monday 12 June 2017, 15:00-16:00

Program Slicing for High-level synthesis

User Shane Fleming (Imperial College).

House Level 9 Seminar Room, EE Dept..

Monday 15 May 2017, 15:00-16:00

Input-dependent Static Timing Analysis (iSTA)

User Andrea Suardi (Imperial College).

House Level 9 Seminar Room, EE Dept..

Monday 08 May 2017, 15:00-16:00

FPGA -Based Acceleration of RankNet for Web Search

User Qiang Li.

House Level 9 Seminar Room, EE Dept..

Monday 24 April 2017, 15:00-16:00

Adventures in Signal Selection

User James Davis (Imperial College).

House Level 9 Seminar Room, EE Dept..

Monday 27 March 2017, 15:00-16:00

Implementing an arbitrary number of iterations to arbitrary precision

User He Li (Imperial College).

House Level 9 Seminar Room, EE Dept..

Monday 20 March 2017, 15:00-16:00

Communication-Aware MCMC Method for Big Data Applications on FPGAs

User Steven Liu.

House Room 610B, EEE Building.

Monday 13 March 2017, 15:00-16:00

A High-Performance System-on-Chip Architecture for Direct Tracking and SLAM

User Konstantinos Boikos (Imperial College).

House Room 610B, EEE Building.

Monday 06 March 2017, 15:00-16:00

Automatically Comparing Memory Consistency Models

User John Wickerson (Imperial College).

House Room 610B, EEE Building.

Monday 13 February 2017, 15:00-16:00

Hardware Synthesis of Weakly Consistent C Concurrency

User Nadesh Ramanathan (Imperial College).

House IBE Meeting Room 1.

Monday 06 February 2017, 15:00-16:00

fpgaConvNet: Automated Design Space Exploration for FPGA-based Convolutional Neural Networks

User Stelios I. Venieris (Imperial College London).

House Room 610B, EEE Building.

Monday 23 January 2017, 15:00-16:00

SysAlloc2: Three-Stage Memory Allocator for Heterogeneous Systems

User Hilda Xue (CAS).

House Room 610B, EEE Building.

Monday 16 January 2017, 15:00-16:00

A look into the Intel FPGA SDK for OpenCL

User Joshua M Levine (Imperial College).

House Level 9 Mahanakorn Lab., EEE Dept..

Monday 12 December 2016, 15:00-16:00

TALK POSTPONED - NO TALK THIS WEEK

User Joshua M Levine (Imperial College).

House Level 9 Mahanakorn Lab., EEE Dept..

Monday 05 December 2016, 15:00-16:00

HiPC Practice Talk: Balancing locality and concurrency: solving sparse triangular systems on GPUs'

User Andrea Picciau (Imperial College).

House Level 9 Mahanakorn Lab., EEE Dept..

Monday 28 November 2016, 15:00-16:00

An Efficient Implementation of Online Arithmetic

User Aaron Zhao (Former BEng Student at Imperial, now MPhil Student at Cambridge).

House 144 Huxley Building, DoC.

Monday 21 November 2016, 15:00-16:00

HiPEDS Seminar - Automatically Comparing Memory Consistency Models

User Dr John Wickerson, EEED.

House 144 Huxley Building, DoC.

Wednesday 26 October 2016, 12:00-13:00

Power to the People

User James Davis (Imperial College).

House Level 9 Mahanakorn Lab., EEE Dept..

Monday 10 October 2016, 15:00-16:00

Title to be confirmed

User Qiang Li (Imperial College).

House Dennis Gabor Seminar Room (611), EEE Department.

Monday 05 September 2016, 15:00-16:00

Automatically Comparing Memory Consistency Models

User John Wickerson (Imperial College).

House Level 9 Mahanakorn Lab., EEE Dept..

Monday 15 August 2016, 15:00-16:00

NEURAL NETWORK BASED REINFORCEMENT LEARNING ACCELERATION ON FPGA PLATFORMS

User Jiang Su (Imperial College).

House Level 9 Mahanakorn Lab., EEE Dept..

Friday 22 July 2016, 14:00-15:00

FPL2016 Practice Talk

User Konstantinos Boikos (Imperial College).

House Level 9 Mahanakorn Lab., EEE Dept..

Tuesday 19 July 2016, 14:00-15:00

Neural Network Based Reinforcement Learning Acceleration on FPGA Platforms

User Jiang Su (Imperial College).

House Level 9 Mahanakorn Lab., EEE Dept..

Monday 18 July 2016, 15:00-16:00

Large Scale Configurable Clouds

User Doug Burger (Microsoft).

House Dennis Gabor Seminar Room (611), EEE Department.

Friday 27 May 2016, 11:00-12:00

StitchUp: Automatic Control Flow Protection for High Level Synthesis Circuits

User Shane Fleming (Imperial College).

House Level 9 Mahanakorn Lab., EEE Dept..

Monday 23 May 2016, 13:00-14:00

FCCM 2016 - Debrief

User Speaker to be confirmed.

House Dennis Gabor Seminar Room (611), EEE Department.

Monday 16 May 2016, 13:00-14:00

FCCM 2016 - Practice Talks

User Speaker to be confirmed.

House Dennis Gabor Seminar Room (611), EEE Department.

Wednesday 27 April 2016, 16:00-18:00

Loop Splitting for Efficient Pipelining in High-Level Synthesis (FCCM '16 practice talk)

User Junyi Liu.

House Level 9 Mahanakorn Lab., EEE Dept..

Monday 25 April 2016, 12:30-13:30

Whole Systems Energy Transparency (or: More Power to Software Developers!)

User Kerstin Eder (University of Bristol).

House Dennis Gabor Seminar Room (611), EEE Department.

Wednesday 13 April 2016, 14:00-15:00

FPGAs in the Datacenter at Microsoft

User Aaron Smith (Microsoft).

House Dennis Gabor Seminar Room (611), EEE Department.

Monday 21 March 2016, 14:00-15:00

ARC 2016 - Practice Talk

User Marlon Wijeyasinghe.

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 17 March 2016, 10:00-11:00

FPGA 2016 - Debrief

User Speaker to be confirmed.

House Level 9 Mahanakorn Lab., EE Dept..

Monday 14 March 2016, 15:00-16:00

FPGA 2016 - Practice Talks

User Xitong Gao and Nadesh Ramanathan.

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 11 February 2016, 14:00-15:00

Better Pipelining in High-level Synthesis

User Junyi Liu.

House Level 9 Mahanakorn Lab., EE Dept..

Monday 18 January 2016, 15:00-16:00

Custom-Sized Caches in Application-Specific Memory Hierarchies (FPT practice talk)

User Felix Winterstein (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Wednesday 02 December 2015, 15:00-16:00

A Multi-Codec Framework to Enhance Data Channels in FPGA Streaming Systems

User Marlon Wijeyasinghe.

House Level 9 Mahanakorn Lab., EE Dept..

Monday 30 November 2015, 15:00-16:00

Using an FPGA SoC to accelerate semi-dense embedded SLAM applications

User Konstantinos Boikos (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Monday 09 November 2015, 15:00-16:00

Title to be confirmed

User Liucheng Guo (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Monday 26 October 2015, 15:00-16:00

Heterogeneous Multi-Processor Pipelines: a Real-Time MPSoC Story

User Sri Parameswaran (University of New South Wales).

House Denis Gabor Seminar Room, 611.

Friday 23 October 2015, 11:00-12:00

Accelerating Non-Linear SVM Training on FPGAs

User Mudhar Bin Rabieah (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Monday 19 October 2015, 15:00-16:00

Trading between task-level and data-level parallelism to solve sparse triangular linear systems

User Andrea Picciau (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Monday 12 October 2015, 15:00-16:00

The logic of MOSFET logic

User Dan Ghica (University of Birmingham).

House EEE Department, Room 503.

Friday 09 October 2015, 11:30-12:30

An Exact MCMC Accelerator Under Custom Precision Regimes

User Shuanglong Liu (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Monday 05 October 2015, 14:00-15:00

StitchUp: Protecting the Control-Flow of HLS Circuits Through Program Slicing

User Shane Fleming (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Monday 28 September 2015, 14:00-15:00

Title to be confirmed

User Andrea Suardi (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Monday 21 September 2015, 14:00-15:00

Title to be confirmed

User Xitong Gao (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Monday 14 September 2015, 14:00-15:00

FPL practice talk

User Stelios I. Venieris (Imperial College London).

House Level 9 Mahanakorn Lab., EE Dept..

Friday 28 August 2015, 14:00-15:00

FPL practice talk

User Hilda Xue (CAS).

House Level 9 Mahanakorn Lab., EE Dept..

Monday 24 August 2015, 11:30-12:30

Portable, Predictable and Partitionable: A Domain Specific approach to Heterogeneous Computing

User Gordon Inggs (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Monday 27 July 2015, 11:30-12:30

Bending Quartus II to Your Will!

User Joshua M Levine (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Monday 20 July 2015, 11:30-12:30

Design of Approximate Overclocked Datapath

User Kan Shi (Imperial College).

House Dennis Gabor Seminar Room 611, EE Dept..

Monday 13 July 2015, 11:30-12:30

From C to FPGA proptotype with TCL scripts

User Andrea Suardi (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Monday 29 June 2015, 11:30-12:30

Optimal Co-design of FPGA Implementations for MPC

User Bulat Khusainov.

House Level 9 Mahanakorn Lab., EE Dept..

Monday 22 June 2015, 11:30-12:30

Low Overhead Mitigation of Radiation Effects in SRAM-Based FPGAs for Avionics

User Michail Vavouras (Imperial College London).

House Level 9 Mahanakorn Lab., EE Dept..

Monday 15 June 2015, 11:30-12:30

SysAlloc: Bringing Malloc/Free to Heterogeneous Systems

User Hilda Xue (CAS).

House Level 9 Mahanakorn Lab., EE Dept..

Monday 08 June 2015, 11:30-12:30

The CProver Program Analysis Tools

User Oxford.

House EEE Department, Room 503.

Tuesday 02 June 2015, 11:00-12:00

Computing in the Deep

User Stelios Venieris.

House Level 9 Mahanakorn Lab., EE Dept..

Monday 01 June 2015, 11:30-12:30

OpenCL for FPGAs

User Gordon Inggs (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Monday 11 May 2015, 11:30-12:30

Discussion on FPGA implementation of decision tree predicting process in the context of incremental decision tree induction

User Chuan Cheng (Imperial College London).

House Level 9 Mahanakorn Lab., EE Dept..

Monday 27 April 2015, 11:30-12:30

PushPush: Seamless Integration of HW and SW Objects Via Function Calls Over AXI

User Ivan Beretta (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Monday 20 April 2015, 11:30-12:30

FCCM '15 practice talk

User Liucheng Guo (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Tuesday 31 March 2015, 13:00-14:00

Particle MCMC acceleration for large-scale inference in genetics using FPGAs

User Grigorios Mingas (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Monday 30 March 2015, 11:30-12:30

FPGA'15 debrief

User Multiple speakers.

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 19 March 2015, 14:00-15:00

MATCHUP: Memory Abstractions for Heap Manipulating Programs - FPGA'15 Practice Talk

User Felix Winterstein (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 19 February 2015, 11:00-12:00

Delay-Bounded Routing for Shadow Registers (dry-run for FPGA15)

User Eddie Hung (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 12 February 2015, 14:30-15:30

CypherDB: A Novel Architecture for Outsourcing Secure Database Processing

User Hung Chen (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Monday 09 February 2015, 11:30-12:30

Thoughts in Distributing Homogeneous Computations on FPGAs: A Case Study of Artificial Neural Networks

User Jiang Su (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Monday 02 February 2015, 11:30-12:30

FPT '14 debrief

User Multiple speakers.

House Level 9 Mahanakorn Lab., EE Dept..

Monday 26 January 2015, 11:30-12:30

Bridging the gap between networking and end-host computing

User Noa Zilberman (University of Cambridge).

House Level 9 Mahanakorn Lab., EE Dept..

Monday 19 January 2015, 11:30-12:30

Title to be confirmed

User Oghenevworhe Joan Omeru (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Monday 08 December 2014, 11:30-12:30

FPT '14 practice talk (Part 2)

User Shuanglong Liu and Aryan Tavakkoli (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 04 December 2014, 10:00-11:30

Loop Pipelining in High-level Synthesis

User Junyi Liu (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Monday 01 December 2014, 11:30-12:30

FPT '14 practice

User Gordon Iggs, Kan Shi, Shuanglong Liu.

House Level 9 Mahanakorn Lab., EE Dept..

Tuesday 25 November 2014, 09:00-11:15

High-level synthesis of stochastic circuits

User Jason Anderson.

House Level 9 Mahanakorn Lab., EE Dept..

Monday 24 November 2014, 11:30-12:30

New Applications of Moment-SOS hierarchies

User Victor Magron (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Monday 17 November 2014, 11:30-12:30

Low-latency option pricing using systolic binomial trees

User Aryan Tavakkoli (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Monday 03 November 2014, 11:30-12:30

Tutorial: Developing OpenCV applications with VivadoHLS generated coprocessors on the Zynq platform

User Shane Fleming (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Monday 27 October 2014, 11:30-12:30

Title to be confirmed

User Edward A Stott (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Monday 29 September 2014, 11:00-12:00

Robust explicit MPC design under finite precision arithmetic

User Andrea Suardi (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Monday 22 September 2014, 11:00-12:00

FPL 2014 debrief

User Multiple speakers.

House Level 9 Mahanakorn Lab., EE Dept..

Monday 15 September 2014, 11:00-12:00

Automated Framework for FPGA-Based Parallel Genetic Algorithms

User Liucheng Guo (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Monday 25 August 2014, 11:00-12:00

Getting started with HLS for Compute: Maxeler MaxCompiler, Xilinx Vivado HLS and Altera OpenCL SDK

User Gordon Inggs (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Monday 18 August 2014, 11:00-12:00

Design and Optimization for Energy-Efficient Fault-Tolerant Systems

User Rong Ye (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Monday 28 July 2014, 11:00-12:00

A Scalable approach for Data Assimilation methods

User Rossella Arcucci.

House Level 9 Mahanakorn Lab., EE Dept..

Monday 21 July 2014, 11:00-12:00

Accelerating Finite Element Methods on FPGA

User Pavel Burovskiy (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Monday 14 July 2014, 11:00-12:00

Practical Techniques for Auto-Active Verification

User Dr Nadia Polikarpova, ETH Zurich.

House Room 503, EEE.

Tuesday 08 July 2014, 11:00-12:00

Practical Techniques for Auto-Active Verification

User Nadia Polikarpova.

House Room 217, Department of Computing.

Tuesday 08 July 2014, 11:00-12:00

DAC '14 debrief

User Kan Shi (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Monday 30 June 2014, 11:00-12:00

Accelerator technology for structured mixed-integer programming problems (ESA practice)

User Andrea Picciau (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Monday 23 June 2014, 11:00-12:00

To Infinity... and Beyond!

User George A Constantinides (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Monday 16 June 2014, 11:00-12:00

Realisability Interpretation and Rule Schemata

User Caroline Hou, Dept. of Computer Science, University of Swansea.

House Mahanakorn Lab, EEE.

Friday 13 June 2014, 12:00-12:30

Templates and Higher Level Synthesis

User Peter Ogden (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Monday 09 June 2014, 11:00-12:00

Parallel resampling for Particle Filters on FPGAs

User Shuanglong Liu (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Monday 02 June 2014, 11:00-12:00

DAC14 practice talk

User Kan Shi (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Friday 30 May 2014, 13:30-14:30

FCCM '14 debrief

User Joshua M Levine (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Friday 23 May 2014, 14:00-15:00

SDK4FPGA: an Open Source framework to optimal design, easily validate and fast prototyping an algorithm on FPGA

User Andrea Suardi (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Wednesday 21 May 2014, 11:00-12:00

OPS-SAT: How will commercial FPGAs cope in space?

User Shane Fleming and Felix Winterstein (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Wednesday 07 May 2014, 11:00-12:00

Separation Logic-Assisted Code Transformations for Efficient High-Level Synthesis

User Felix Winterstein (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Tuesday 06 May 2014, 10:00-11:00

Fast FPGA prototyping: an application of Fast Gradient Method to audio signal processing

User Andrea Suardi (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Tuesday 18 March 2014, 10:00-11:00

How Often Is Floating-Point Addition Non-Associative?

User Theo Drane (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Friday 07 March 2014, 16:00-17:00

Zero Overhead FPGA Instrumentation

User Eddie Hung (Imperial College).

House Level 11 Control Seminar room, room 1109a, EE Dept..

Tuesday 04 March 2014, 12:00-13:00

"PEACH2: an FPGA switching fabric for high performance computing"

User Takaaki Miyajima (Miya).

House Level 9 Mahanakorn Lab., EE Dept..

Friday 21 February 2014, 16:00-17:00

FPGA '14 practice talk

User Joshua M Levine (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 20 February 2014, 13:00-14:00

Timing Fault Detection in FPGAs

User Edward A Stott (Imperial College).

House Level 9 Mahanakorn Lab., EEE Dept..

Wednesday 29 January 2014, 11:00-12:00

The Many Lives of an FPGA DSP Block

User Suhaib Fahmy (Nanyang Technological University).

House Level 9 Mahanakorn Lab., EEE Dept..

Wednesday 08 January 2014, 15:00-16:00

Master Thesis: FPGA Implementation of An Interior Point Method for High-speed Model Predictive Control

User Junyi Liu (Imperial College).

House Level 9 Mahanakorn Lab., EEE Dept..

Wednesday 08 January 2014, 11:00-12:00

CAS IT presentation

User Gordon Inggs (Imperial College).

House Level 9 Mahanakorn Lab., EEE Dept..

Thursday 05 December 2013, 14:00-15:00

FPT practice talk – Exploiting Stochastic Delay Variability on FPGAs with Adaptive Partial Rerouting

User Justin Wong (Imperial College London).

House Room 610B, EEE Department.

Friday 29 November 2013, 14:00-15:00

Balancing Higher-Order Convergence and Architectural Efficiency for Finite-Difference Methods

User Oghenevworhe Joan Omeru (Imperial College).

House Level 9 Mahanakorn Lab., EEE Dept..

Wednesday 13 November 2013, 11:00-12:00

Practical skills for digital electronics researchers : useful software glue

User Samuel Bayliss (Imperial College).

House Level 9 Mahanakorn Lab., EEE Dept..

Wednesday 16 October 2013, 11:00-12:00

Optical Communications Overview and FPGA-based DSP

User Christos Spatharakis (Photonics Communications Research Lab - NTUA Athens).

House Level 9 Mahanakorn Lab., EE Dept..

Tuesday 15 October 2013, 15:00-16:00

Optical Communications Overview and FPGA-based DSP

User Christos Spatharakis, Photonics Communications Research Lab at NTUA, Athens.

House Level 9 Mahanakorn Lab., EEE Dept..

Tuesday 15 October 2013, 15:00-16:00

A polynomial time algorithm for word-length optimisation

User Karthick Parashar (Impeial College, CAS).

House Level 9 Mahanakorn Lab., EEE Dept..

Wednesday 25 September 2013, 14:00-15:00

FPL 2013 Debrief Session

User Multiple speakers.

House Room 503, EEE Department.

Thursday 12 September 2013, 14:00-15:00

The Case for Embedded NoCs on FPGAs

User Vaughn Betz, University of Toronto.

House Level 9 Mahanakorn Lab., EE Dept..

Friday 30 August 2013, 11:00-12:00

Beyond the Event Driven Paradigm - Introducing the Migen FHDL library

User Sébastien Bourdeauducq.

House Dennis Gabor Seminar Room (611), EEE Department.

Thursday 29 August 2013, 12:00-13:00

FPL practice talk

User Felix Winterstein (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Wednesday 14 August 2013, 12:30-13:30

Progressive sampling of image data in hardware systems

User Jianxiong Liu (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Wednesday 10 July 2013, 11:00-12:00

Energy Efficient Computing System - Research in NICS CAD Tsinghua

User Yu Wang (Tsinghua University, China).

House Level 9 Mahanakorn Lab., EE Dept..

Tuesday 09 July 2013, 11:00-12:00

Toward accurate polynomial evaluation in rounded arithmetic

User Theo Drane (Imperial College).

House Room 610B, EEE Department.

Friday 28 June 2013, 11:00-12:00

Making Heterogeneous Computing Accessible

User Gordon Inggs (CAS, Imperial College London).

House Level 9 Mahanakorn Lab., EE Dept..

Wednesday 19 June 2013, 11:00-12:00

Structural Optimization of Arithmetic Expressions for High-Level Synthesis

User Xitong Gao (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Wednesday 12 June 2013, 11:00-12:00

Exploiting Algorithm-based Fault Tolerance for Reliability in Parallel Accelerators

User James Davis (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Wednesday 29 May 2013, 11:00-12:00

FCCM '13 Debrief

User Multiple speakers.

House Level 9 Mahanakorn Lab., EE Dept..

Friday 17 May 2013, 11:00-12:00

ISCAS Practce Talk

User Kan Shi (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Tuesday 14 May 2013, 11:00-12:00

FPGA fast prototyping with LabVIEW and Vivado HLS

User Andrea Suardi and Felix Winterstein (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Tuesday 14 May 2013, 10:00-11:00

Accelerating the training process of Random Forest classifier on FPGA

User Chuan Cheng (Imperial College London).

House Level 9 Mahanakorn Lab., EE Dept..

Wednesday 01 May 2013, 11:00-12:00

Per-path Physical Timing analysis tool for arbitrary circuits on FPGA

User Justin Wong (Imperial College London).

House Level 9 Mahanakorn Lab., EE Dept..

Wednesday 24 April 2013, 11:00-12:00

FCCM practice talks

User Multiple speakers.

House Level 9 Mahanakorn Lab., EE Dept..

Monday 22 April 2013, 10:00-13:00

FCCM practice

User Grigorios Mingas (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Wednesday 17 April 2013, 11:00-12:00

Fault recovery through dynamic partial reconfiguration in FPGA-based systems and TMR as a protection method from SEUs in FPGAs

User Michail Vavouras (Imperial College London).

House Level 9 Mahanakorn Lab., EE Dept..

Wednesday 10 April 2013, 11:00-12:00

BERI - an open source 64-bit processor for multicore research

User Simon Moore (Cambridge).

House Level 9 Mahanakorn Lab., EE Dept..

Wednesday 27 March 2013, 11:00-12:00

Real-Time Image Processing with Catapult-C

User Rui Duarte (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Wednesday 13 March 2013, 11:00-12:00

ARC practice: Fast matrix multiplication over small finite fields

User Shane Fleming (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Tuesday 12 March 2013, 10:00-11:00

Git: Introduction and Tutorial

User Peter Ogden (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Wednesday 27 February 2013, 11:00-12:00

Co-design of embedded MPC controllers

User Andrea Suardi (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Wednesday 20 February 2013, 11:00-12:00

A Joint Framework for Face Super-Resolution

User Yonggang Jin (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Wednesday 06 February 2013, 11:00-12:00

FPGA 2013 Practice talk: Word-length Optimization Beyond Straight Line Code

User David P Boland (Imperial College).

House Dennis Gabor Seminar Room (611), EEE Department.

Monday 04 February 2013, 14:00-15:00

A VARIATION-AWARE RETIMING METHOD EXPLOITING RECONFIGURABILITY

User Zhenyu Guan.

House Level 9 Mahanakorn Lab., EE Dept..

Wednesday 30 January 2013, 11:00-12:00

The Arts and Crafts of Quartus II

User Joshua M Levine (Imperial College).

House Dennis Gabor Seminar Room (611), EEE Department.

Wednesday 12 December 2012, 11:00-12:00

Compiling functional-imperative languages into hardware

User Dan Ghica.

House Seminar Room, Level 11, EEE Department.

Tuesday 11 December 2012, 12:00-13:00

Highlights from ICCAD 2012: Where's the Tofu?

User Samuel Bayliss (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Wednesday 05 December 2012, 11:00-12:00

Optimal Control of an Atomic Force Microscope on an FPGA using the Fast Gradient Method

User Juan Jerez Fullana (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Wednesday 28 November 2012, 11:00-12:00

Control and Power Seminars

Algorithms and computer architectures for efficient real-time optimization and linear algebra solvers

User E. Kerrigan, Imperial College London.

Wednesday 21 November 2012, 14:00-15:00

Optimizing the arithmetic precision of MCMC algorithms

User Grigorios Mingas (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Wednesday 21 November 2012, 11:00-12:00

EDA Club Open Day: FMCAD for CAS

User David P Boland (Imperial College).

House Room 610B, EEE Department.

Thursday 15 November 2012, 15:00-16:00

Some approaches to the static analysis of programs

User David Monniaux (VERIMAG).

House Dennis Gabor Seminar Room (611), EEE Department.

Wednesday 14 November 2012, 11:00-12:00

Multi-level Monte Carlo Simulation with Mixed Floating-point Precision

User Zhiyong Liu (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 08 November 2012, 11:00-12:00

Using Training Statistics for Prediction Adjustment in Regression Forests

User Adam Powell (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Wednesday 07 November 2012, 11:00-12:00

Float to Float Function Approximation

User David B Thomas (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Wednesday 31 October 2012, 11:00-12:00

Some Experiments in Scala

User George A Constantinides (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Friday 19 October 2012, 11:00-12:00

Error-tolerant software adaptation of signal processing systems

User Yiannis Andreopoulos.

House Room 503, Level 5, EEE Dept. .

Thursday 18 October 2012, 16:00-17:00

System-level approaches for fixed-point refinement of signal processing algorithms

User Karthick Parashar (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Wednesday 10 October 2012, 11:00-12:00

Theo's Toolkit Wishlist

User Theo Drane (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 04 October 2012, 11:00-12:00

Overclocking Datapath for Latency-Error Tradeoff

User Kan Shi (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 13 September 2012, 13:00-14:00

FPL 2012 Debrief

User Nachiket Kapre.

House Level 9 Mahanakorn Lab., EE Dept..

Monday 10 September 2012, 13:00-14:00

Atlantica 2012 - Talk 7 - RIFFA

User Farhan Rahman.

House Level 9 Mahanakorn Lab., EE Dept..

Wednesday 05 September 2012, 18:00-18:15

Atlantica 2012 - Talk 6 - Lanczos++

User Abid Rafique.

House Level 9 Mahanakorn Lab., EE Dept..

Wednesday 05 September 2012, 17:00-17:45

Atlantica 2012 - Talk 5 - SAT Solvers

User Andrew Bean.

House Level 9 Mahanakorn Lab., EE Dept..

Wednesday 05 September 2012, 16:15-17:00

Atlantica 2012 - Talk 4 - Matrix-Free SPICE

User Coryan Wilson-Shah.

House Level 9 Mahanakorn Lab., EE Dept..

Wednesday 05 September 2012, 15:30-16:15

Atlantica 2012 - Talk 3 - Understanding Multi-Kernel GPU Execution

User Dulitha.

House Level 9 Mahanakorn Lab., EE Dept..

Wednesday 05 September 2012, 14:45-15:30

Atlantica 2012 - Talk 2 - Matrix Factorization Acceleration

User Siddhartha.

House Level 9 Mahanakorn Lab., EE Dept..

Wednesday 05 September 2012, 14:00-14:45

Atlantica 2012 - Talk 1 - AutoESL Graph Machine Mapping

User Gordon Inggs (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Wednesday 05 September 2012, 11:00-11:45

Reduced Complexity Tone Classifier for Automatic Tonal Speech Recognizer

User Jirabhorn Chaiwongsai (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 30 August 2012, 13:00-14:00

Hardware Assisted Security in Cloud Computing

User Hung Chen (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Wednesday 29 August 2012, 11:00-12:00

FPL practice talk #2

User Abid Rafique (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Friday 24 August 2012, 15:00-16:00

Graph Machine Practice Talk

User Gordon Inggs.

House Level 9 Mahanakorn Lab., EE Dept..

Friday 24 August 2012, 14:00-15:00

Software for Research - Day 4 - Signal Processing

User Dr. Eduardo Aguilar Pelaez (Imperial College London).

House Level 9 Mahanakorn Lab., EE Dept..

Friday 24 August 2012, 11:00-12:00

Software For Research - Day 3 - Compute Cluster Management

User Imperial College London.

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 23 August 2012, 14:00-15:00

Software for Research - Day 2 - C++ STL

User Peter Ogden.

House Level 9 Mahanakorn Lab., EE Dept..

Wednesday 22 August 2012, 11:00-12:00

Software for Research - Day 1 - Result Analytics

User Andrew Bean and Zhenyu Guan.

House Level 9 Mahanakorn Lab., EE Dept..

Tuesday 21 August 2012, 11:00-12:00

Enhancing Performance of Tall-Skinny QR Factorization using FPGAs

User Abid Rafique (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 16 August 2012, 13:00-14:00

Title to be confirmed

User Andrew Bean (Imperial College London).

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 09 August 2012, 13:00-14:00

Beyond worst-case clocking of circuits

User Edward A Stott (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 19 July 2012, 13:00-14:00

YAIOCM - Yet another invitation-only coding marathon

User Nachiket Kapre (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Friday 13 July 2012, 11:00-17:00

vfscaling coding 10k run (invitation-only)

User Nachiket Kapre (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 12 July 2012, 13:00-17:00

Coding Marathon #4

User Nachiket Kapre.

House Level 9 Mahanakorn Lab., EE Dept..

Friday 06 July 2012, 11:00-17:00

Coding Marathon #3 (Reuse old invitation)

User Nachiket Kapre.

House Level 9 Mahanakorn Lab., EE Dept..

Friday 29 June 2012, 11:00-17:00

Coding Marathon #2 (Reuse old Invitation)

User Nachiket Kapre.

Friday 22 June 2012, 12:00-17:00

Blurring boundaries: using software verification methodologies in hardware design

User David P Boland (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 21 June 2012, 13:00-14:00

Transfer presentation

User Rui Duarte (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Wednesday 20 June 2012, 15:30-16:00

Coding Marathon (Invitation-Only)

User Nachiket Kapre (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Friday 15 June 2012, 11:00-17:00

Context-based vision processing system

User Jianxiong Liu (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 14 June 2012, 13:00-14:00

DeSyRe - On Demand System Reliability

User Michail Vavouras (Imperial College London).

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 07 June 2012, 13:00-14:00

Monte Carlo Simulation On FPGA Implementation

User Zhiyong Liu (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 31 May 2012, 13:00-14:00

Software Engineering Best Practices for High-Impact Research

User Peter Ogden (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Friday 25 May 2012, 11:00-12:00

Optimal Hardware Implementation of an Optimal Controller

User Andrea Suardi (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 24 May 2012, 13:00-14:00

Greener Search: FPGA Acceleration of Real-time Unstructured Search

User Wim Vanderbauwhede, University of Glasgow.

House Level 9 Mahanakorn Lab., EE Dept..

Wednesday 23 May 2012, 11:00-12:00

Integer Point Counting Techniques for Polyhedra

User Samuel Bayliss (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 17 May 2012, 13:00-14:00

Converting Existing Software to Hardware using SynphonyCC: A Case Study of an Open Source Connect-6 Solver

User Sumanta Chaudhuri (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 10 May 2012, 13:00-14:00

High-Level Frequency Variation Aware Optimization of Linear Projections for FPGAs

User Rui Duarte (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 26 April 2012, 13:00-14:00

FCCM practice

User Juan Jerez Fullana & Grigorios Mingas (Imperial College London) .

House Level 9 Mahanakorn Lab., EE Dept..

Wednesday 25 April 2012, 16:00-17:00

OpenCPI/SCORE Progress Meeting

User Speaker to be confirmed.

House Level 9 Mahanakorn Lab., EE Dept..

Monday 23 April 2012, 17:00-18:00

Helene's FCCM 2012 Practice

User Speaker to be confirmed.

House Level 9 Mahanakorn Lab., EE Dept..

Friday 20 April 2012, 17:00-18:00

Nachiket's Group Meeting

User Nachiket Kapre (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Friday 13 April 2012, 12:30-13:30

Lanczos on FPGA - ARC Talk Take #2

User Abid Rafique.

House Level 9 Mahanakorn Lab., EE Dept..

Tuesday 03 April 2012, 11:00-12:00

FPGA CONNECT NoC generator

User Speaker to be confirmed.

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 29 March 2012, 18:30-19:30

System Optimization Techniques for Hardware Compiler

User Dr. Sujit Bhattacharya (Imperial College London).

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 29 March 2012, 13:00-14:00

Assorted student talks

User Speaker to be confirmed.

House Level 9 Mahanakorn Lab., EE Dept..

Wednesday 28 March 2012, 11:00-15:00

Courier: A Domain Specific Language and Toolchain for Runtime Binary Acceleration

User Takaaki Miyajima, Keio University, Japan.

House Mahanakorn Conference room, level 9.

Friday 23 March 2012, 13:00-14:00

An Efficient FPGA-based Design for Programmable Ion Channel Simulations

User Graeme Coapes (Newcastle University).

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 22 March 2012, 13:00-14:00

ASPLOS/FPGA 2012 Debrief

User Nachiket Kapre.

House Denis Gabor Seminar Room, 611.

Friday 16 March 2012, 13:00-14:00

Face Super-Resolution

User Yonggang Jin (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 15 March 2012, 13:00-14:00

Classification of variation maps: An efficient technique to combat process variation in FPGAs

User Zhenyu Guan (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Tuesday 13 March 2012, 14:30-15:30

ARC '12 practice

User Grigoris Mingas & Abid Rafique (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 08 March 2012, 13:00-14:00

Performance Prediction of Image Compression Methods on Soft Processors

User Adam Powell (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 01 March 2012, 13:00-14:00

FPGA 2012 Practice

User Nikil Mehta.

House Level 9 Mahanakorn Lab., EE Dept..

Monday 20 February 2012, 15:30-16:30

CAS Seminar on FPGA Variability, and Architecture (Guest speaker from Japan)

User Justin Wong, Zhenyu Guan (Imperial College) and Dr. Kazuya Tanigawa (Hiroshima City University, Japan).

House EEE Room 611 (Gabor Seminar Room).

Thursday 16 February 2012, 11:00-13:30

Increasing the efficiency and accessibility of next-generation computing platforms

User Lesley Shannon (Simon Fraser University).

House Room 503, EE Dept..

Tuesday 14 February 2012, 16:00-17:00

NTU Seminar Practice #2

User Nachiket Kapre (Imperial College).

House Huxley 218.

Thursday 09 February 2012, 17:00-18:00

Mesh NoCs with Bluespec

User Blithe.

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 02 February 2012, 14:30-15:30

NTU Seminar Practice #1

User Nachiket Kapre (Imperial College).

House EEE Room 611.

Thursday 02 February 2012, 11:00-12:00

'Sharpening the Ax' - development of the Rhino System

User Gordon Inggs (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 26 January 2012, 13:00-14:00

Title to be confirmed

User Theo Drane (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 19 January 2012, 13:00-14:00

FPT 2011 Debrief

User Nachiket Kapre (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Monday 16 January 2012, 11:00-12:00

Feasibility of accelerating random forest using FPGA

User Chuan Cheng (Imperial College London).

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 12 January 2012, 13:00-14:00

Asynchronous circuits for High-performance Energy Minimum Operation

User Ben Devlin, University of Tokyo.

House Level 9 Mahanakorn Lab., EEE Dept..

Friday 09 December 2011, 13:00-14:00

A Reliability Carol: Detecting the Ghost of Errors Past, Present and Future

User Joshua M Levine (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 08 December 2011, 13:00-14:00

Sparse Matrix-Solve Unroll

User Siddhartha.

House Level 9 Mahanakorn Lab., EE Dept..

Monday 05 December 2011, 13:00-13:15

Dummy

User Abid Rafique (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Monday 05 December 2011, 12:15-13:00

Survey of Learning and Adaptation Algorithms for Potential FPGA Mapping

User Andrew Bean.

House Level 9 Mahanakorn Lab., EE Dept..

Monday 05 December 2011, 12:00-12:15

VLIW-SCORE (FPT 2011 2nd practice)

User Nachiket Kapre (Imperial College).

House Level 9 Mahanakorn Lab., EEE Dept..

Monday 05 December 2011, 11:00-12:00

Approaching the Peak GPU Performance in FPGAs for Scientific Computing

User Juan Jerez Fullana (Imperial College London).

House Room 503, EE Dept..

Friday 25 November 2011, 12:00-13:00

VLIW-SCORE (FPT2011 Raw Practice)

User Nachiket Kapre (Imperial College).

House Level 9 Mahanakorn Lab., EEE Dept..

Friday 25 November 2011, 11:00-12:00

FPT'11 Practice Talk (Timing Speculation in FPGAs: Probabilistic Inference of Data Dependent Failure Rates)

User Sumanta Chaudhuri and Justin Wong (Imperial College).

House Room 503, EE Dept..

Thursday 24 November 2011, 12:00-13:00

A reliability-aware design methodology for embedded systems on multi-FPGA platforms

User Chiara Sandionigi (Politecnico di Milano).

House Level 9 Mahanakorn Lab., EE Dept..

Monday 14 November 2011, 14:00-15:00

The VENICE Soft Vector Processor

User Guy Lemieux (UBC).

House Level 9 Mahanakorn Lab., EE Dept..

Monday 14 November 2011, 11:00-12:00

OpenCPI - an open source framework for component-based development in heterogeneous processing embedded systems

User James Kulp, Parera Information Services and Shepard Siegel, Atomic Rules.

House Level 9 Mahanakorn Lab., EE Dept..

Friday 11 November 2011, 16:00-17:00

Fixed Point Refinement: A systems approach

User Karthick Parashar (IRISA).

House Level 9 Mahanakorn Lab., EE Dept..

Tuesday 01 November 2011, 14:00-15:00

Optimization through GPGPUs

User Gabriel Caffarena (University CEU San Pablo).

House Level 9 Mahanakorn Lab., EE Dept..

Friday 28 October 2011, 11:00-12:00

FPGA implementation of Parallel Tempering MCMC

User Grigoris Mingas (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 27 October 2011, 13:00-14:00

Designing optimal digital hardware using the Polytope Model

User Samuel Bayliss (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 20 October 2011, 13:00-14:00

Fixed-point explicit MPC in FPGAs

User Andrea Suardi (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 13 October 2011, 13:00-14:00

FPL '11 Debrief

User Edward A Stott (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Tuesday 13 September 2011, 10:00-11:00

Computing with Streams in SCORE

User Nachiket Kapre (Imperial College).

House Room 503/EEE.

Friday 09 September 2011, 11:00-13:00

Imperial-Penn Series: MSc Student Project Presentations

User Speaker to be confirmed.

House Level 9 Mahanakorn Lab., EE Dept..

Tuesday 06 September 2011, 14:00-16:00

Title to be confirmed

User Rui Duarte (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Tuesday 30 August 2011, 10:00-11:00

Improving FPGA reliability with wear-levelling (FPL practice)

User Ed Stott, CAS Group.

House Level 9 Mahanakorn Lab., EE Dept..

Tuesday 23 August 2011, 10:00-11:00

OpenCPI Experiences for ML605 Board

User Udit and Albert.

House Room 503/EEE.

Friday 19 August 2011, 14:00-15:00

Can you quote the b-Ax norm as a measure of how well you solved Ax=b?

User David P Boland and Bianca Furtuna (Imperial College) .

House Level 9 Mahanakorn Lab., EE Dept..

Friday 19 August 2011, 10:00-11:00

Imperial-Penn Group Meeting

User Speaker to be confirmed.

House Level 9 Mahanakorn Lab., EE Dept..

Tuesday 16 August 2011, 16:00-18:00

Visual memory aided image enhancement

User Jianxiong Liu (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Tuesday 02 August 2011, 10:00-11:00

Imperial-Penn Group Meeting

User Speaker to be confirmed.

House Level 9 Mahanakorn Lab., EE Dept..

Tuesday 26 July 2011, 16:00-17:00

FPGA implementation of Viola&Jones face detector with dynamic workload balancing

User Chuan Cheng (Imperial College London).

House Room 503/EEE.

Tuesday 26 July 2011, 10:00-11:00

Imperial CAS Reading Group

User Josh Levine and Nachiket Kapre.

House Room 503/EEE.

Friday 22 July 2011, 12:00-13:00

GraphStep: Compute Model and Programming Tutorial

User Nachiket Kapre (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Friday 15 July 2011, 13:00-15:00

Nachiket's MSc Student Talks (Continued)

User Speaker to be confirmed.

House Level 9 Mahanakorn Lab., EE Dept..

Tuesday 12 July 2011, 13:00-14:00

Multiprocessor Scheduling, Resource Allocation and Numerical Data Representation

User Sujit Bhattacharya (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Tuesday 12 July 2011, 10:00-11:00

Imperial CAS Reading Group

User Alex Casson and Theo Drane.

House Room 503/EEE.

Friday 08 July 2011, 12:00-13:30

Nachiket's MSc Student Group Presentation #2

User Helene Martorell, Emmanouil Spanakis, Fang Zhou and Wei Lizhong.

House Room 503.

Monday 04 July 2011, 13:00-15:00

CAS Brainstorming (Variation / Reliability)

User Speaker to be confirmed.

House Gabor Seminar Room, Level 6, EEE.

Monday 04 July 2011, 10:00-16:00

ISCA/PLDI Debrief

User Nachiket Kapre.

House Room 503/EEE.

Friday 01 July 2011, 15:00-16:00

Imperial-Penn Group Meeting

User Rafi Rubin and Zhenyu Guan.

House Room 503/EEE.

Tuesday 28 June 2011, 16:00-18:00

A Run-time Adaptive FPGA Architecture for Monte Carlo Simulations

User Xiang Tian (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Tuesday 28 June 2011, 10:00-11:00

Smartphone Power Amplifier Circuit Design

User Kasra Omid-Zohoor, PhD student at Stanford University.

House Gabor lecture room, 611 EE Dept..

Thursday 23 June 2011, 14:00-15:00

Title to be confirmed

User Theo Drane (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Tuesday 21 June 2011, 10:00-11:00

Real-Time Memory-Adaptive Image Compression for Resource-Constrained Systems

User Adam Powell (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Tuesday 14 June 2011, 10:00-11:00

A Sparse and Condensed QP Formulation for Predictive Control

User Juan Jerez Fullana (Imperial College London).

House Level 9 Mahanakorn Lab., EE Dept..

Tuesday 07 June 2011, 10:00-11:00

GPU Code-Generation Extensions to the SCORE Compiler

User Cody Huang.

House Level 9 Mahanakorn Lab., EE Dept..

Wednesday 01 June 2011, 13:00-14:00

Imperial CAS Reading Group

User Speaker to be confirmed.

House Room 503/EEE.

Tuesday 31 May 2011, 12:00-13:00

Markov Chain Monte Carlo using reconfigurable hardware - the effect of limited precision

User Grigorios Mingas (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Tuesday 31 May 2011, 10:00-11:00

Imperial-Penn Group Meeting

User Speaker to be confirmed.

House Level 9 Mahanakorn Lab., EE Dept..

Tuesday 24 May 2011, 16:00-18:00

Explicit Model Predictive Control in FPGAs

User Andrea Suardi (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Tuesday 24 May 2011, 10:00-11:00

Imperial CAS Reading Group

User Speaker to be confirmed.

House Room 503/EEE.

Wednesday 18 May 2011, 14:00-15:00

SPICE Next Steps

User Nachiket Kapre (Imperial College London).

House Level 9 Mahanakorn Lab., EE Dept..

Tuesday 17 May 2011, 10:00-11:00

Imperial-Penn Group Meeting

User Speaker to be confirmed.

House Level 9 Mahanakorn Lab., EE Dept..

Tuesday 10 May 2011, 17:00-19:00

Circuit characterization towards high-level circuit design optimization

User Rui Duarte (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Tuesday 10 May 2011, 10:00-11:00

Towards accelerating primal-dual interior point method for solving large-scale Semi-Definite Programs

User Abid Rafique (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Friday 06 May 2011, 10:00-11:00

Imperial CAS Reading Group

User nachiket@imperial.ac.uk.

House Room 503/EEE.

Wednesday 04 May 2011, 12:30-14:00

Membrane Computing and More

User David Kearney (University of South Australia).

House Level 9 Mahanakorn Lab., EE Dept..

Wednesday 27 April 2011, 14:00-15:00

Compiling with the Value State Dependence Graph

User James Stanier (Sussex).

House Level 9 Mahanakorn Lab., EE Dept..

Wednesday 27 April 2011, 13:00-14:00

Imperial-Penn Group Meeting

User Speaker to be confirmed.

House Level 9 Mahanakorn Lab., EE Dept..

Tuesday 12 April 2011, 17:00-18:00

Introduction to face detection methods

User Chuan Cheng (Imperial College London).

House Room 503/EEE.

Monday 04 April 2011, 11:30-12:00

ARC 2011 Conference Debrief

User Nachiket Kapre (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Wednesday 30 March 2011, 14:00-15:00

Imperial-UPenn Group Meeting on FPGA Variation/Aging

User Speaker to be confirmed.

House Level 9 Mahanakorn Lab., EE Dept..

Tuesday 22 March 2011, 16:00-18:00

The Challenges of Writing Portable, Correct and High Performance Libraries for GPUs or How to Avoid the Heroics of GPU Programming

User Miriam Leeser (Northeastern University, USA).

House Gabor Room 611, EEE.

Monday 21 March 2011, 12:00-13:00

Symbolic evaluation of GPU software

User David Huw Jones (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Monday 21 March 2011, 11:30-12:00

Application Specific Memory Access, Reuse and Reordering for SDRAM

User Samuel Bayliss (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Monday 21 March 2011, 10:00-11:00

FPGA 2011 Debrief

User Nachiket Kapre (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Tuesday 08 March 2011, 15:00-16:00

No longer available

User Theo Drane (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Monday 07 March 2011, 13:00-14:00

Optimize massively parallel stochastic difference simulations

User Xiang Tian (Imperial College London).

House Level 9 Mahanakorn Lab., EE Dept..

Monday 07 March 2011, 11:30-12:00

Resource-Constrained Object-Based Compression for Surveillance Systems

User Adam Powell (Imperial College London).

House Level 9 Mahanakorn Lab., EE Dept..

Monday 28 February 2011, 11:30-12:00

An FPGA Implementation of a Sparse Quadratic Programming Solver for Constrained Predictive Control

User Juan (Imperial College London).

House Level 9 Mahanakorn Lab., EE Dept..

Wednesday 23 February 2011, 14:00-14:30

PPoPP/HPCA Conference Debrief

User Nachiket Kapre (Imperial College London).

House Level 9 Mahanakorn Lab., EE Dept..

Tuesday 22 February 2011, 13:00-14:00

Bio-inspired visual memory: a report on the motivation and methodology

User Jian Xiong Liu (Imperial College London).

House Level 9 Mahanakorn Lab., EE Dept..

Monday 21 February 2011, 11:30-12:00

Markov Chain Monte Carlo using reconfigurable hardware

User Grigoris Mingas (Imperial College London).

House Level 9 Mahanakorn Lab., EE Dept..

Monday 14 February 2011, 11:30-12:00

Implementation of a Haar-like feature classifier based on an FPGA

User Chuan Cheng (Imperial College London).

House Level 9 Mahanakorn Lab., EE Dept..

Monday 07 February 2011, 11:30-12:00

Probabilistic Computing: A Case Study of Ripple Carry Adders

User Sumanta Chaudhuri (Imperial College).

House Room 503/EEE.

Tuesday 01 February 2011, 12:00-12:00

Playing with Polynomials and Precision

User David P Boland (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Wednesday 12 January 2011, 16:00-17:00

Configurable Electronic Architectures for the Treatment of Complex Mathematical Models

User Andrea Suardi.

House Room 503/EEE.

Friday 19 November 2010, 10:00-11:00

Towards Analytical Methods for FPGA Architecture Investigation

User Steve Wilton (University of British Columbia).

House Huxley Building, 344A.

Thursday 04 November 2010, 16:00-17:00

Just a Minute! : Exploiting memory access patterns without repetition, hesitation or deviation

User Samuel Bayliss (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 28 October 2010, 13:00-14:00

Towards Hardware Acceleration of Semi-Definite Programming (SDP) Solver targeting Sum Of Squares (SOS) Optimization Problem

User Abid Rafique (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Monday 04 October 2010, 13:00-14:00

No longer available

User Theo Drane (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Friday 24 September 2010, 15:00-16:00

Protecting your work for commercial opportunities

User Andrew Barber (Imperial College).

House Mahanakorn Lab, L9, EEE.

Monday 20 September 2010, 16:00-16:45

POSTPONED

User Samuel Bayliss (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 09 September 2010, 16:00-17:00

POSTPONED: Protecting your work for commercial opportunities

User Andrew Barber (Imperial College).

House Mahanakorn Lab, L9, EEE.

Monday 06 September 2010, 14:00-14:45

MPC for Deeply Pipelined FPGA Implementation

User Juan (Imperial College London).

House Level 9 Mahanakorn Lab., EE Dept..

Tuesday 24 August 2010, 15:30-16:30

POSTPONED

User Abid Rafique (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 22 July 2010, 13:00-14:00

Title to be confirmed

User David P Boland (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 15 July 2010, 16:00-17:00

Incremental and Verified Modelling of the PCI Express Protocol

User Peter Boehm.

House Mahanakorn Lab, L9, EEE.

Wednesday 30 June 2010, 15:00-16:00

No longer available

User Theo Drane (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 24 June 2010, 15:00-16:00

Designing Parameterised Application Specific SDRAM controllers from Affine Loop Nests

User Samuel Bayliss (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 03 June 2010, 16:00-17:00

FCCM 2010: Automated Precision Analysis: A Polynomial Algebraic Approach

User David P Boland (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Tuesday 11 May 2010, 12:00-13:00

Sampling and Controlling Faster than the Computational Delay

User Dominic Buchstaller (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 22 April 2010, 16:00-17:00

The impact of resonant, distributed, frequency and transmission properties of interconnects upon nano-scale VLSI devices reliability and functionality

User Pavel Livshits.

House Level 9 Mahanakorn Lab., EE Dept..

Monday 22 March 2010, 14:00-15:00

TALK POSTPONED

User Dominic Buchstaller (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Monday 22 March 2010, 13:00-14:00

Power consumption modelling of FPGAs

User Alastair Smith (Imperial College London).

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 11 March 2010, 16:00-17:00

A Unified Data Parallel Programming Model for Multicore Processors, GPUs and FPGA Circuits

User Satnam Singh (Microsoft Research Cambridge).

House Dennis Gabor Seminar Room 611, EE Dept..

Thursday 11 March 2010, 12:00-13:00

MASSIVELY PARALLEL PROCESSOR ARRAY: AN FPGA REPLACEMENT?

User Guy Lemieux (UBC).

House Gabor Seminar Room (Room 611).

Monday 08 March 2010, 16:00-17:00

ARC 2010: Keynote Preview

User Professor Peter Cheung (Imperial College London).

House Room 503/EEE.

Wednesday 03 March 2010, 14:30-15:00

ARC2010: Optimising Memory Bandwidth Use for Matrix-Vector Multiplication in Iterative Methods

User David P Boland (Imperial College).

House Room 503/EEE.

Wednesday 03 March 2010, 14:00-14:30

ARC2010: A Fused Hybrid Floating-Point and Fixed-Point Dot-product for FPGAs

User Antonio Roldao Lopes (PhD at IC).

House Room 503/EEE.

Wednesday 03 March 2010, 13:30-14:00

ARC2010: Design of a Financial Application Driven Multivariate Gaussian Random Number Generator for an FPGA

User Chalermpol Saiprasert (Imperial College).

House Room 503/EEE.

Wednesday 03 March 2010, 13:00-13:30

TALK POSTPONED

User Dominic Buchstaller (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 25 February 2010, 16:00-17:00

Degradation in FPGAs: Measurement and Modelling

User Ed Stott, CAS Group.

House Room 908/EEE.

Monday 15 February 2010, 14:00-15:00

A Hybrid Floating-point and Fixed-point Dot-product Design for FPGAs

User Antonio Roldao Lopes (PhD at IC).

House Level 9 Mahanakorn Lab., EE Dept..

Monday 08 February 2010, 15:00-16:00

Hardware design of MPC controllers

User Juan (Imperial College London).

House Level 9 Mahanakorn Lab., EE Dept..

Monday 25 January 2010, 15:00-16:00

No longer available

User Theo Drane (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 10 December 2009, 13:00-14:00

Mini FPT: "Automatic Optimisation of MapReduce Designs by Geometric Programming"

User Qiang Liu (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Tuesday 01 December 2009, 14:15-14:45

Mini FPT: "Performance Comparison of GPU and FPGA Architectures for the SVM Training Problem"

User Speaker to be confirmed.

House Level 9 Mahanakorn Lab., EE Dept..

Tuesday 01 December 2009, 14:00-14:15

Mini FPT: "Methodology for Designing Statically Scheduled Application-Specific SDRAM Controllers using Constrained Local Search"

User Samuel Bayliss (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Tuesday 01 December 2009, 13:45-14:00

Mini FPT: "Modelling degradation in FPGA lookup tables"

User Edward A Stott (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Tuesday 01 December 2009, 13:30-13:45

Mini FPT: "Concurrently optimising FPGA architectures and transistor sizing: implications for FPGA design"

User Alastair Smith (Imperial College London).

House Level 9 Mahanakorn Lab., EE Dept..

Tuesday 01 December 2009, 13:00-13:30

Title to be confirmed

User Samuel Bayliss (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 26 November 2009, 13:00-14:00

The Role of Computer-Assisted Numerical Proofs in Efficient Hardware Design

User George A Constantinides (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 12 November 2009, 13:00-14:00

CANCELLED

User None.

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 12 November 2009, 12:00-13:00

Self-Hosted Placement for Massively Parallel Processor Arrays

User Guy Lemieux, University of British Columbia, Vancouver, Canada.

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 29 October 2009, 15:00-16:00

Optimising Memory Bandwidth Use for Matrix-Vector Multiplication in Iterative Methods

User David P Boland (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 29 October 2009, 13:00-14:00

FPGA Architecture Optimisation Using Geometric Programming

User Alastair Smith (Imperial College London).

House Level 9 Mahanakorn Lab., EE Dept..

Wednesday 21 October 2009, 14:00-15:00

Robust Stability and Performance for Multiple Model Switched Adaptive Control

User Dominic Buchstaller (Imperial College).

House Denis Gabor Seminar Room, 611.

Wednesday 21 October 2009, 13:00-14:00

Accelerating the dot-product operation using Field Programmable Gate Arrays

User Antonio Roldao Lopes (PhD at IC).

House Room 611, EEE.

Thursday 01 October 2009, 12:00-13:00

Area Estimation and Optimisation of FPGA Routing Fabrics

User Alastair Smith (Imperial College London).

House Level 9 Mahanakorn Lab., EE Dept..

Wednesday 19 August 2009, 09:00-10:00

System Design – Leveraging Capability, Overcoming Complexity

User Suhaib Fahmy (Imperial College London).

House Room 611, EEE.

Thursday 06 August 2009, 13:00-14:00

Methodology for Designing Statically Scheduled Application-Speciﬁc SDRAM Controllers using Constrained Local Search

User Sam Bayliss.

House Room 611, EEE.

Thursday 06 August 2009, 12:00-13:00

Heterogeneous architecture exploration using analytical tools and VPR 5.0

User Asma Kahoul (Imperial College).

House Room 611, EEE.

Thursday 23 July 2009, 12:00-13:00

Predicting Bounds on Ranges of Variables in an Algorithm using Polynomials

User David P Boland (Imperial College).

House Room 611, EEE.

Friday 10 July 2009, 12:00-13:00

What is Web 2.0 and how it changes almost everything!

User Antonio Roldao (PhD@IC).

House Mahanakorn Lab, L9, EEE.

Thursday 14 May 2009, 14:30-15:30

What is Web 2.0 and how it changes almost everything!

User Antonio Roldao (PhD@IC).

House Dennis Gabor Seminar Room (611), EEE Department.

Thursday 14 May 2009, 14:30-15:30

TIADC Mismatch Compensation

User Prof Lim Yong Ching (Nanyang Technological University, Singapore) .

House Room 611, EEE.

Thursday 14 May 2009, 11:00-12:00

Parallel Computation of the Phylogenetic Likelihood Kernel in HW and SW

User Dr. Alexandros Stamatakis, Exelixis Lab, Department of Computer Science, Technische Universitat Munchen.

House Level 9 Mahanakorn Lab., EE Dept..

Tuesday 31 March 2009, 14:30-15:30

Static scheduling of SDRAM commands using constraint logic programming

User Sam Bayliss (Imperial College London).

House Level 9 Mahanakorn Lab., EE Dept..

Wednesday 25 March 2009, 12:00-13:00

FCCM Preview: More FLOPS or More Precision? Accuracy Parameterizable Linear Equation Solvers for Model Predictive Control

User Antonio Roldao (PhD@IC).

House Level 9 Mahanakorn Lab., EE Dept..

Monday 23 March 2009, 14:30-15:00

MRSC Preview: An FPGA-Based Floating Point Solver for Band Structured Linear Equations

User Antonio Roldao (PhD@IC).

House Level 9 Mahanakorn Lab., EE Dept..

Monday 23 March 2009, 14:00-14:30

ARC: Practice Talk 2

User Asma Kahoul (Imperial College London).

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 12 March 2009, 12:00-13:00

ARC Preview: Word-length Optimization and Error Analysis of a Multivariate Gaussian Random Number Generator

User Paul Saiprasert (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 05 March 2009, 15:45-16:15

ARC Preview: Heterogeneous Architecture Exploration: Analysis vs Parameter Sweep

User Asma Kahoul (Imperial College London).

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 05 March 2009, 15:00-15:30

Challenges in FPGA Research

User Dr Peter Jamieson (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 26 February 2009, 12:00-13:00

Multiplication Without Multipliers: Algorithms, Applications, and Extensions

User Dr Oscar Gustafsson (Linkoping University).

House Level 9 Mahanakorn Lab., EE Dept..

Friday 20 February 2009, 12:00-12:45

Challenges in FPGA Research

User Dr Peter Jamieson (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 19 February 2009, 12:30-13:00

Predicting minimal error bounds through an algorithm

User David Boland ( Imperial College London).

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 19 February 2009, 12:00-12:30

More FLOPS or more precision? Accuracy Parameterizable Linear Equation Solvers for Model-Predictive Control

User Antonio Roldao (PhDatIC).

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 05 February 2009, 12:00-13:00

Fixed-Point Arithmetic in DSP

User Dr George A Constantinides (Imperial College London).

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 22 January 2009, 16:00-17:00

FPGA architecture optimisation using geometric programming

User Alastair Smith (Imperial College London).

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 22 January 2009, 12:00-13:00

Transforming image processing algorithms for efficient FPGA implementation

User Donald Bailey, Massey University, New Zealand.

House Level 9 Mahanakorn Lab., EE Dept..

Wednesday 21 January 2009, 11:00-12:00

FPT Report-Back

User Antonio Roldao (PhD@IC).

House Dennis Gabor Seminar Room (611), EEE Department.

Wednesday 17 December 2008, 15:00-15:30

Best Papers of Autumn Term

User Several.

House Dennis Gabor Seminar Room (611), EEE Department.

Wednesday 17 December 2008, 14:00-15:00

'A linear algebra framework for automatic determination of optimal data layouts' by Mahmut Kandemir et al.

User Sam Bayliss (Imperial College London).

House Room 503/EEE.

Wednesday 17 December 2008, 12:00-12:30

Heterogeneous Architecture Exploration: Analysis vs. Parameter sweep

User Asma Kahoul (Imperial College London).

House Level 9 Mahanakorn Lab., EE Dept..

Monday 01 December 2008, 12:00-13:00

(FPT Preview) Optimizing Coarse-Grained Units in Floating Point Hybrid FPGAs

User Chi Wai Yu, Department of Computing, Imperial College London.

House Level 9 Mahanakorn Lab., EE Dept..

Friday 28 November 2008, 16:00-16:30

(FPT Preview) Modelling and Compensating for Clock Skew Variability in FPGAs

User Dr Pete Sedcole (Imperial College London).

House Level 9 Mahanakorn Lab., EE Dept..

Friday 28 November 2008, 15:30-16:00

(FPT Preview) A Transition Probability Based Delay Measurement Method for Arbitrary Circuits on FPGAs

User Justin Wong (Imperial College London).

House Level 9 Mahanakorn Lab., EE Dept..

Friday 28 November 2008, 15:00-15:30

(FPT Preview) A Scalable FPGA Architecture for Non-linear SVM Training

User Markos Papadonikolakis (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Friday 28 November 2008, 12:00-13:00

(FPT Preview) Co-optimisation of Datapath and Memory in Outer Loop Pipelining

User Kieron Turkington (Imperial College London).

House Level 9 Mahanakorn Lab., EE Dept..

Friday 28 November 2008, 11:00-12:00

CG: Optimizing FPGA Speed using Custom Precision

User Antonio Roldao (PhD@IC).

House Level 9 Mahanakorn Lab., EE Dept..

Wednesday 19 November 2008, 14:00-15:00

Improving Real-time Observability in Embedded Logic Analysis

User Nicola Nicolici (McMaster University, Canada).

House Dennis Gabor Seminar Room (611), EEE Department.

Friday 07 November 2008, 16:00-17:00

COMMSYN: On-Chip Communication Architecture Synthesis for Multi-Processor Systems-on-Chip

User Prof Nikil Dutt (University of California, Irvine).

House Dennis Gabor Seminar Room (611), EEE Department.

Friday 07 November 2008, 11:30-12:30

On Logical Masking Effects of Soft Errors

User Prof. Sudhakar M. Reddy (University Of Iowa, USA).

House Dennis Gabor Seminar Room (611), EEE Department.

Friday 07 November 2008, 10:30-11:30

A New Approach for Exploring Numerical Accuracy

User David Boland ( Imperial College London).

House Level 9 Mahanakorn Lab., EE Dept..

Monday 03 November 2008, 12:00-13:00

Wirelength Modeling for Homogeneous and Heterogeneous FPGA Architectural Development

User Alastair Smith (Imperial College London).

House Level 9 Mahanakorn Lab., EE Dept..

Monday 20 October 2008, 12:00-13:00

Accelerating Iterative Methods Using FPGAs

User Antonio Roldao (PhD@IC).

House Level 9 Mahanakorn Lab., EE Dept..

Tuesday 07 October 2008, 14:00-15:00

Developing analytical techniques for FPGA architecture design

User Alastair Smith (Imperial College London).

House Level 9 Mahanakorn Lab., EE Dept..

Monday 06 October 2008, 11:00-12:00

Some Ideas from my Sabbatical

User Dr George A Constantinides (Imperial College London).

House Level 9 Mahanakorn Lab., EE Dept..

Wednesday 24 September 2008, 10:00-11:00

Fault Tolerance and Reliability in FPGAs

User Edward Stott (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Wednesday 20 August 2008, 14:00-15:00

Memory and Datapath optimisation for FPGA co-processors

User Kieron Turkington (Imperial College London).

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 14 August 2008, 14:00-15:00

Four Important Concepts to Consider when Using Multicore Clusters

User Dr George A Constantinides (Imperial College London).

House Level 9 Mahanakorn Lab., EE Dept..

Monday 11 August 2008, 11:30-12:30

Combining Data Reuse Exploitation with Data-Level Parallelization for FPGA-Targeted Hardware Compilation: A Geometric Programming Framework

User Qiang Liu, Imperial College London.

House Level 9 Mahanakorn Lab., EE Dept..

Tuesday 05 August 2008, 12:15-13:00

An FPGA-based Implementation of the MINRES Algorithm

User David Boland, Imperial College London.

House Level 9 Mahanakorn Lab., EE Dept..

Tuesday 05 August 2008, 11:30-12:15

Efficient FPGA Mapping of Gilbert's Algorithm for SVM Training on Large-Scale Classification Problems

User Markos Papadonikolakis (Imperial College).

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 31 July 2008, 11:30-12:30

Report from RSSI

User David Boland ( Imperial College London).

House Level 9 Mahanakorn Lab., EE Dept..

Tuesday 15 July 2008, 15:00-15:30

Compiling C-like Languages to FPGA Hardware: Some Novel Approaches Targeting Data Memory Organisation

User Qiang Liu, Imperial College London.

House Level 9 Mahanakorn Lab., EE Dept..

Tuesday 15 July 2008, 14:00-15:00

Low-Power Design for Reconfigurable Computing

User Dr George A Constantinides (Imperial College London).

House Level 9 Mahanakorn Lab., EE Dept..

Tuesday 15 July 2008, 11:30-12:30

Investigating I/O and Memory Bandwidth trade-offs for Iterative Algorithms

User David Boland, Imperial College London.

House Level 9 Mahanakorn Lab., EE Dept..

Thursday 03 July 2008, 12:00-13:00

From the Horse's Mouth - Architecture of Stratix III

User Vaughn Betz, Altera Corp.

House Room 611, EEE.

Tuesday 01 July 2008, 11:00-12:00

If you have a question about this list, please contact: George A Constantinides; Dr Christos Bouganis; Wiesia R Hsissen. If you have a question about a specific talk, click on that talk to find its organiser.

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